2 * Copyright (C) 2008 Renesas Solutions Corp.
3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 /* PRI control register */
14 #define PRPRICR5 0xFF800048 /* LMB */
15 #define PRPRICR5_D 0x2a
18 #define FPGA_NAND_CTL 0xB410020C
19 #define FPGA_NAND_RST 0x0008
20 #define FPGA_NAND_INIT 0x0000
21 #define FPGA_NAND_RST_WAIT 10000
48 /* Pin Function Controler data */
49 #define PSELA_D 0x1410
50 #define PSELB_D 0x0140
51 #define PSELC_D 0x0000
52 #define PSELD_D 0x0400
54 /* I/O Buffer Hi-Z data */
55 #define HIZCRA_D 0x0000
56 #define HIZCRB_D 0x1000
57 #define HIZCRC_D 0x0000
58 #define HIZCRD_D 0x0000
60 /* Module select reg data */
61 #define MSELCRA_D 0x0014
62 #define MSELCRB_D 0x0018
64 /* Module Stop reg Data */
65 #define MSTPCR2_D 0xFFD9F280
68 extern void init_cpld(void);
72 puts("BOARD: AP325RXA\n");
78 /* Pin Function Controler Init */
84 /* I/O Buffer Hi-Z Init */
85 outw(HIZCRA_D, HIZCRA);
86 outw(HIZCRB_D, HIZCRB);
87 outw(HIZCRC_D, HIZCRC);
88 outw(HIZCRD_D, HIZCRD);
90 /* Module select reg Init */
91 outw(MSELCRA_D, MSELCRA);
92 outw(MSELCRB_D, MSELCRB);
94 /* Module Stop reg Init */
95 outl(MSTPCR2_D, MSTPCR2);
122 /* PRI control register Init */
123 outl(PRPRICR5_D, PRPRICR5);
131 void led_set_state(unsigned short value)
135 void ide_set_reset(int idereset)
137 outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
138 udelay(FPGA_NAND_RST_WAIT);
139 outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
142 int board_eth_init(bd_t *bis)
145 #ifdef CONFIG_SMC911X
146 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);