2 * Copyright (C) 2008 Renesas Solutions Corp.
3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 /* PRI control register */
16 #define PRPRICR5 0xFF800048 /* LMB */
17 #define PRPRICR5_D 0x2a
20 #define FPGA_NAND_CTL 0xB410020C
21 #define FPGA_NAND_RST 0x0008
22 #define FPGA_NAND_INIT 0x0000
23 #define FPGA_NAND_RST_WAIT 10000
50 /* Pin Function Controler data */
51 #define PSELA_D 0x1410
52 #define PSELB_D 0x0140
53 #define PSELC_D 0x0000
54 #define PSELD_D 0x0400
56 /* I/O Buffer Hi-Z data */
57 #define HIZCRA_D 0x0000
58 #define HIZCRB_D 0x1000
59 #define HIZCRC_D 0x0000
60 #define HIZCRD_D 0x0000
62 /* Module select reg data */
63 #define MSELCRA_D 0x0014
64 #define MSELCRB_D 0x0018
66 /* Module Stop reg Data */
67 #define MSTPCR2_D 0xFFD9F280
70 extern void init_cpld(void);
74 puts("BOARD: AP325RXA\n");
80 /* Pin Function Controler Init */
86 /* I/O Buffer Hi-Z Init */
87 outw(HIZCRA_D, HIZCRA);
88 outw(HIZCRB_D, HIZCRB);
89 outw(HIZCRC_D, HIZCRC);
90 outw(HIZCRD_D, HIZCRD);
92 /* Module select reg Init */
93 outw(MSELCRA_D, MSELCRA);
94 outw(MSELCRB_D, MSELCRB);
96 /* Module Stop reg Init */
97 outl(MSTPCR2_D, MSTPCR2);
124 /* PRI control register Init */
125 outl(PRPRICR5_D, PRPRICR5);
135 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
136 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
137 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
141 void led_set_state(unsigned short value)
145 void ide_set_reset(int idereset)
147 outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
148 udelay(FPGA_NAND_RST_WAIT);
149 outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
152 int board_eth_init(bd_t *bis)
155 #ifdef CONFIG_SMC911X
156 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);