git.sur5r.net Git - u-boot/blob - board/renesas/r0p7734/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   3  * Copyright (C) 2011 Renesas Solutions Corp.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <config.h>
   8 #include <asm/processor.h>
   9 #include <asm/macro.h>
  10
  11 #include <asm/processor.h>
  12
  13         .global lowlevel_init
  14
  15         .text
  16         .align  2
  17
  18 lowlevel_init:
  19
  20         /* WDT */
  21         write32 WDTCSR_A, WDTCSR_D
  22
  23         /* MMU */
  24         write32 MMUCR_A, MMUCR_D
  25
  26         write32 FRQCR2_A, FRQCR2_D
  27         write32 FRQCR0_A, FRQCR0_D
  28
  29         write32 CS0CTRL_A, CS0CTRL_D
  30         write32 CS1CTRL_A, CS1CTRL_D
  31         write32 CS0CTRL2_A, CS0CTRL2_D
  32
  33         write32 CSPWCR0_A, CSPWCR0_D
  34         write32 CSPWCR1_A, CSPWCR1_D
  35         write32 CS1GDST_A, CS1GDST_D
  36
  37         # clock mode check
  38         mov.l   MODEMR, r1
  39         mov.l   @r1, r0
  40         and             #6, r0 /* Check 1 and 2 bit.*/
  41         cmp/eq  #2, r0 /* 0x02 is 533Mhz mode */
  42         bt      init_lbsc_533
  43
  44 init_lbsc_400:
  45
  46         write32 CSWCR0_A, CSWCR0_D_400
  47         write32 CSWCR1_A, CSWCR1_D
  48
  49         bra     init_dbsc3_400_pad
  50         nop
  51
  52         .align 2
  53
  54 MODEMR:         .long   0xFFCC0020
  55 WDTCSR_A:       .long   0xFFCC0004
  56 WDTCSR_D:       .long   0xA5000000
  57 MMUCR_A:        .long   0xFF000010
  58 MMUCR_D:        .long   0x00000004
  59
  60 FRQCR2_A:       .long   0xFFC80008
  61 FRQCR2_D:       .long   0x00000000
  62 FRQCR0_A:       .long   0xFFC80000
  63 FRQCR0_D:       .long   0xCF000001
  64
  65 CS0CTRL_A:      .long   0xFF800200
  66 CS0CTRL_D:      .long   0x00000020
  67 CS1CTRL_A:      .long   0xFF800204
  68 CS1CTRL_D:      .long   0x00000020
  69
  70 CS0CTRL2_A:     .long   0xFF800220
  71 CS0CTRL2_D:     .long   0x00004000
  72
  73 CSPWCR0_A:      .long   0xFF800280
  74 CSPWCR0_D:      .long   0x00000000
  75 CSPWCR1_A:      .long   0xFF800284
  76 CSPWCR1_D:      .long   0x00000000
  77 CS1GDST_A:      .long   0xFF8002C0
  78 CS1GDST_D:      .long   0x00000011
  79
  80 init_lbsc_533:
  81
  82         write32 CSWCR0_A, CSWCR0_D_533
  83         write32 CSWCR1_A, CSWCR1_D
  84
  85         bra     init_dbsc3_533_pad
  86         nop
  87
  88         .align 2
  89
  90 CSWCR0_A:       .long   0xFF800230
  91 CSWCR0_D_533:   .long   0x01120104
  92 CSWCR0_D_400:   .long   0x02120114
  93 /* CSWCR0_D_400:        .long   0x01160116 */
  94 CSWCR1_A:       .long   0xFF800234
  95 CSWCR1_D:       .long   0x077F077F
  96 /* CSWCR1_D_400:        .long   0x00120012 */
  97
  98 init_dbsc3_400_pad:
  99
 100         write32 DBPDCNT3_A,     DBPDCNT3_D
 101         wait_timer      WAIT_200US_400
 102
 103         write32 DBPDCNT0_A,     DBPDCNT0_D_400
 104         write32 DBPDCNT3_A,     DBPDCNT3_D0
 105         write32 DBPDCNT1_A,     DBPDCNT1_D
 106
 107         write32 DBPDCNT3_A,     DBPDCNT3_D1
 108         wait_timer WAIT_32MCLK
 109
 110         write32 DBPDCNT3_A,     DBPDCNT3_D2
 111         wait_timer WAIT_100US_400
 112
 113         write32 DBPDCNT3_A,     DBPDCNT3_D3
 114         wait_timer WAIT_16MCLK
 115
 116         write32 DBPDCNT3_A,     DBPDCNT3_D4
 117         wait_timer WAIT_200US_400
 118
 119         write32 DBPDCNT3_A,     DBPDCNT3_D5
 120         wait_timer WAIT_1MCLK
 121
 122         write32 DBPDCNT3_A,     DBPDCNT3_D6
 123         wait_timer WAIT_10KMCLK
 124
 125         bra init_dbsc3_ctrl_400
 126         nop
 127
 128         .align 2
 129
 130 init_dbsc3_533_pad:
 131
 132         write32 DBPDCNT3_A,     DBPDCNT3_D
 133         wait_timer      WAIT_200US_533
 134
 135         write32 DBPDCNT0_A,     DBPDCNT0_D_533
 136         write32 DBPDCNT3_A,     DBPDCNT3_D0
 137         write32 DBPDCNT1_A,     DBPDCNT1_D
 138
 139         write32 DBPDCNT3_A,     DBPDCNT3_D1
 140         wait_timer WAIT_32MCLK
 141
 142         write32 DBPDCNT3_A,     DBPDCNT3_D2
 143         wait_timer WAIT_100US_533
 144
 145         write32 DBPDCNT3_A,     DBPDCNT3_D3
 146         wait_timer WAIT_16MCLK
 147
 148         write32 DBPDCNT3_A,     DBPDCNT3_D4
 149         wait_timer WAIT_200US_533
 150
 151         write32 DBPDCNT3_A,     DBPDCNT3_D5
 152         wait_timer WAIT_1MCLK
 153
 154         write32 DBPDCNT3_A,     DBPDCNT3_D6
 155         wait_timer      WAIT_10KMCLK
 156
 157         bra init_dbsc3_ctrl_533
 158         nop
 159
 160         .align 2
 161
 162 WAIT_200US_400: .long   40000
 163 WAIT_200US_533: .long   53300
 164 WAIT_100US_400: .long   20000
 165 WAIT_100US_533: .long   26650
 166 WAIT_32MCLK:    .long   32
 167 WAIT_16MCLK:    .long   16
 168 WAIT_1MCLK:             .long   1
 169 WAIT_10KMCLK:   .long   10000
 170
 171 DBPDCNT0_A:             .long   0xFE800200
 172 DBPDCNT0_D_533: .long   0x00010245
 173 DBPDCNT0_D_400: .long   0x00010235
 174 DBPDCNT1_A:             .long   0xFE800204
 175 DBPDCNT1_D:             .long   0x00000014
 176 DBPDCNT3_A:             .long   0xFE80020C
 177 DBPDCNT3_D:             .long   0x80000000
 178 DBPDCNT3_D0:    .long   0x800F0000
 179 DBPDCNT3_D1:    .long   0x800F1000
 180 DBPDCNT3_D2:    .long   0x820F1000
 181 DBPDCNT3_D3:    .long   0x860F1000
 182 DBPDCNT3_D4:    .long   0x870F1000
 183 DBPDCNT3_D5:    .long   0x870F3000
 184 DBPDCNT3_D6:    .long   0x870F7000
 185
 186 init_dbsc3_ctrl_400:
 187
 188         write32 DBKIND_A, DBKIND_D
 189         write32 DBCONF_A, DBCONF_D
 190
 191         write32 DBTR0_A,        DBTR0_D_400
 192         write32 DBTR1_A,        DBTR1_D_400
 193         write32 DBTR2_A,        DBTR2_D
 194         write32 DBTR3_A,        DBTR3_D_400
 195         write32 DBTR4_A,        DBTR4_D_400
 196         write32 DBTR5_A,        DBTR5_D_400
 197         write32 DBTR6_A,        DBTR6_D_400
 198         write32 DBTR7_A,        DBTR7_D
 199         write32 DBTR8_A,        DBTR8_D_400
 200         write32 DBTR9_A,        DBTR9_D
 201         write32 DBTR10_A,       DBTR10_D_400
 202         write32 DBTR11_A,       DBTR11_D
 203         write32 DBTR12_A,       DBTR12_D_400
 204         write32 DBTR13_A,       DBTR13_D_400
 205         write32 DBTR14_A,       DBTR14_D
 206         write32 DBTR15_A,       DBTR15_D
 207         write32 DBTR16_A,       DBTR16_D_400
 208         write32 DBTR17_A,       DBTR17_D_400
 209         write32 DBTR18_A,       DBTR18_D_400
 210
 211         write32 DBBL_A, DBBL_D
 212         write32 DBRNK0_A,       DBRNK0_D
 213
 214         write32 DBCMD_A,        DBCMD_D0_400
 215         write32 DBCMD_A,        DBCMD_D1
 216         write32 DBCMD_A,        DBCMD_D2
 217         write32 DBCMD_A,        DBCMD_D3
 218         write32 DBCMD_A,        DBCMD_D4
 219         write32 DBCMD_A,        DBCMD_D5_400
 220         write32 DBCMD_A,        DBCMD_D6
 221         write32 DBCMD_A,        DBCMD_D7
 222         write32 DBCMD_A,        DBCMD_D8
 223         write32 DBCMD_A,        DBCMD_D9_400
 224         write32 DBCMD_A,        DBCMD_D10
 225         write32 DBCMD_A,        DBCMD_D11
 226         write32 DBCMD_A,        DBCMD_D12
 227
 228         write32 DBBS0CNT1_A,    DBBS0CNT1_D
 229         write32 DBPDNCNF_A,             DBPDNCNF_D
 230
 231         write32 DBRFCNF0_A,     DBRFCNF0_D
 232         write32 DBRFCNF1_A,     DBRFCNF1_D_400
 233         write32 DBRFCNF2_A,     DBRFCNF2_D
 234         write32 DBRFEN_A,       DBRFEN_D
 235         write32 DBACEN_A,       DBACEN_D
 236         write32 DBACEN_A,       DBACEN_D
 237
 238         /* Dummy read */
 239         mov.l DBWAIT_A, r1
 240         synco
 241         mov.l @r1, r0
 242         synco
 243
 244         /* Dummy read */
 245         mov.l SDRAM_A, r1
 246         synco
 247         mov.l @r1, r0
 248         synco
 249
 250         /* need sleep 186A0 */
 251
 252         bra     init_pfc_sh7734
 253         nop
 254
 255         .align 2
 256
 257 init_dbsc3_ctrl_533:
 258
 259         write32 DBKIND_A, DBKIND_D
 260         write32 DBCONF_A, DBCONF_D
 261
 262         write32 DBTR0_A,        DBTR0_D_533
 263         write32 DBTR1_A,        DBTR1_D_533
 264         write32 DBTR2_A,        DBTR2_D
 265         write32 DBTR3_A,        DBTR3_D_533
 266         write32 DBTR4_A,        DBTR4_D_533
 267         write32 DBTR5_A,        DBTR5_D_533
 268         write32 DBTR6_A,        DBTR6_D_533
 269         write32 DBTR7_A,        DBTR7_D
 270         write32 DBTR8_A,        DBTR8_D_533
 271         write32 DBTR9_A,        DBTR9_D
 272         write32 DBTR10_A,       DBTR10_D_533
 273         write32 DBTR11_A,       DBTR11_D
 274         write32 DBTR12_A,       DBTR12_D_533
 275         write32 DBTR13_A,       DBTR13_D_533
 276         write32 DBTR14_A,       DBTR14_D
 277         write32 DBTR15_A,       DBTR15_D
 278         write32 DBTR16_A,       DBTR16_D_533
 279         write32 DBTR17_A,       DBTR17_D_533
 280         write32 DBTR18_A,       DBTR18_D_533
 281
 282         write32 DBBL_A, DBBL_D
 283         write32 DBRNK0_A,       DBRNK0_D
 284
 285         write32 DBCMD_A,        DBCMD_D0_533
 286         write32 DBCMD_A,        DBCMD_D1
 287         write32 DBCMD_A,        DBCMD_D2
 288         write32 DBCMD_A,        DBCMD_D3
 289         write32 DBCMD_A,        DBCMD_D4
 290         write32 DBCMD_A,        DBCMD_D5_533
 291         write32 DBCMD_A,        DBCMD_D6
 292         write32 DBCMD_A,        DBCMD_D7
 293         write32 DBCMD_A,        DBCMD_D8
 294         write32 DBCMD_A,        DBCMD_D9_533
 295         write32 DBCMD_A,        DBCMD_D10
 296         write32 DBCMD_A,        DBCMD_D11
 297         write32 DBCMD_A,        DBCMD_D12
 298
 299         write32 DBBS0CNT1_A,    DBBS0CNT1_D
 300         write32 DBPDNCNF_A,             DBPDNCNF_D
 301
 302         write32 DBRFCNF0_A,     DBRFCNF0_D
 303         write32 DBRFCNF1_A,     DBRFCNF1_D_533
 304         write32 DBRFCNF2_A,     DBRFCNF2_D
 305         write32 DBRFEN_A,       DBRFEN_D
 306         write32 DBACEN_A,       DBACEN_D
 307         write32 DBACEN_A,       DBACEN_D
 308
 309         /* Dummy read */
 310         mov.l DBWAIT_A, r1
 311         synco
 312         mov.l @r1, r0
 313         synco
 314
 315         /* Dummy read */
 316         mov.l SDRAM_A, r1
 317         synco
 318         mov.l @r1, r0
 319         synco
 320
 321         /* need sleep 186A0 */
 322
 323         bra     init_pfc_sh7734
 324         nop
 325
 326         .align 2
 327
 328 DBKIND_A:       .long   0xFE800020
 329 DBKIND_D:       .long   0x00000005
 330 DBCONF_A:       .long   0xFE800024
 331 DBCONF_D:       .long   0x0D030A01
 332
 333 DBTR0_A:        .long   0xFE800040
 334 DBTR0_D_533:.long       0x00000004
 335 DBTR0_D_400:.long       0x00000003
 336 DBTR1_A:        .long   0xFE800044
 337 DBTR1_D_533:.long       0x00000003
 338 DBTR1_D_400:.long       0x00000002
 339 DBTR2_A:        .long   0xFE800048
 340 DBTR2_D:        .long   0x00000000
 341 DBTR3_A:        .long   0xFE800050
 342 DBTR3_D_533:.long       0x00000004
 343 DBTR3_D_400:.long       0x00000003
 344
 345 DBTR4_A:        .long   0xFE800054
 346 DBTR4_D_533:.long       0x00050004
 347 DBTR4_D_400:.long       0x00050003
 348
 349 DBTR5_A:        .long   0xFE800058
 350 DBTR5_D_533:.long       0x0000000F
 351 DBTR5_D_400:.long       0x0000000B
 352
 353 DBTR6_A:        .long   0xFE80005C
 354 DBTR6_D_533:.long       0x0000000B
 355 DBTR6_D_400:.long       0x00000008
 356
 357 DBTR7_A:        .long   0xFE800060
 358 DBTR7_D:        .long   0x00000002 /* common value */
 359
 360 DBTR8_A:        .long   0xFE800064
 361 DBTR8_D_533:.long       0x0000000D
 362 DBTR8_D_400:.long       0x0000000A
 363
 364 DBTR9_A:        .long   0xFE800068
 365 DBTR9_D:        .long   0x00000002 /* common value */
 366
 367 DBTR10_A:       .long   0xFE80006C
 368 DBTR10_D_533:.long      0x00000004
 369 DBTR10_D_400:.long      0x00000003
 370
 371 DBTR11_A:       .long   0xFE800070
 372 DBTR11_D:       .long   0x00000008 /* common value */
 373
 374 DBTR12_A:       .long   0xFE800074
 375 DBTR12_D_533:.long      0x00000009
 376 DBTR12_D_400:.long      0x00000008
 377
 378 DBTR13_A:       .long   0xFE800078
 379 DBTR13_D_533:.long      0x00000022
 380 DBTR13_D_400:.long      0x0000001A
 381
 382 DBTR14_A:       .long   0xFE80007C
 383 DBTR14_D:       .long   0x00070002 /* common value */
 384
 385 DBTR15_A:       .long   0xFE800080
 386 DBTR15_D:       .long   0x00000003 /* common value */
 387
 388 DBTR16_A:       .long   0xFE800084
 389 DBTR16_D_533:.long      0x120A1001
 390 DBTR16_D_400:.long      0x12091001
 391
 392 DBTR17_A:       .long   0xFE800088
 393 DBTR17_D_533:.long      0x00040000
 394 DBTR17_D_400:.long      0x00030000
 395
 396 DBTR18_A:       .long   0xFE80008C
 397 DBTR18_D_533:.long      0x02010200
 398 DBTR18_D_400:.long      0x02000207
 399
 400 DBBL_A: .long   0xFE8000B0
 401 DBBL_D: .long   0x00000000
 402
 403 DBRNK0_A:               .long   0xFE800100
 404 DBRNK0_D:               .long   0x00000001
 405
 406 DBCMD_A:                .long   0xFE800018
 407 DBCMD_D0_533:   .long   0x1100006B
 408 DBCMD_D0_400:   .long   0x11000050
 409 DBCMD_D1:               .long   0x0B000000 /* common value */
 410 DBCMD_D2:               .long   0x2A004000 /* common value */
 411 DBCMD_D3:               .long   0x2B006000 /* common value */
 412 DBCMD_D4:               .long   0x29002004 /* common value */
 413 DBCMD_D5_533:   .long   0x28000743
 414 DBCMD_D5_400:   .long   0x28000533
 415 DBCMD_D6:               .long   0x0B000000 /* common value */
 416 DBCMD_D7:               .long   0x0C000000 /* common value */
 417 DBCMD_D8:               .long   0x0C000000 /* common value */
 418 DBCMD_D9_533:   .long   0x28000643
 419 DBCMD_D9_400:   .long   0x28000433
 420 DBCMD_D10:              .long   0x000000C8 /* common value */
 421 DBCMD_D11:              .long   0x29002384 /* common value */
 422 DBCMD_D12:              .long   0x29002004 /* common value */
 423
 424 DBBS0CNT1_A:    .long   0xFE800304
 425 DBBS0CNT1_D:    .long   0x00000000
 426 DBPDNCNF_A:             .long   0xFE800180
 427 DBPDNCNF_D:             .long   0x00000200
 428
 429 DBRFCNF0_A:             .long   0xFE8000E0
 430 DBRFCNF0_D:             .long   0x000001FF
 431 DBRFCNF1_A:             .long   0xFE8000E4
 432 DBRFCNF1_D_533: .long   0x00000805
 433 DBRFCNF1_D_400: .long   0x00000618
 434
 435 DBRFCNF2_A:             .long   0xFE8000E8
 436 DBRFCNF2_D:             .long   0x00000000
 437
 438 DBRFEN_A:               .long   0xFE800014
 439 DBRFEN_D:               .long   0x00000001
 440
 441 DBACEN_A:               .long   0xFE800010
 442 DBACEN_D:               .long   0x00000001
 443
 444 DBWAIT_A:               .long   0xFE80001C
 445 SDRAM_A:                .long   0x0C000000
 446
 447 init_pfc_sh7734:
 448         write32 PFC_PMMR_A, PFC_PMMR_MODESEL1
 449         write32 PFC_MODESEL1_A, PFC_MODESEL1_D
 450
 451         write32 PFC_PMMR_A, PFC_PMMR_MODESEL2
 452         write32 PFC_MODESEL2_A, PFC_MODESEL2_D
 453
 454         write32 PFC_PMMR_A, PFC_PMMR_IPSR3
 455         write32 PFC_IPSR3_A, PFC_IPSR3_D
 456
 457         write32 PFC_PMMR_A, PFC_PMMR_IPSR4
 458         write32 PFC_IPSR4_A, PFC_IPSR4_D
 459
 460         write32 PFC_PMMR_A, PFC_PMMR_IPSR11
 461         write32 PFC_IPSR11_A, PFC_IPSR11_D
 462
 463         write32 PFC_PMMR_A, PFC_PMMR_GPSR0
 464         write32 PFC_GPSR0_A, PFC_GPSR0_D
 465
 466         write32 PFC_PMMR_A, PFC_PMMR_GPSR1
 467         write32 PFC_GPSR1_A, PFC_GPSR1_D
 468
 469         write32 PFC_PMMR_A, PFC_PMMR_GPSR2
 470         write32 PFC_GPSR2_A, PFC_GPSR2_D
 471
 472         write32 PFC_PMMR_A, PFC_PMMR_GPSR3
 473         write32 PFC_GPSR3_A, PFC_GPSR3_D
 474
 475         write32 PFC_PMMR_A, PFC_PMMR_GPSR4
 476         write32 PFC_GPSR4_A, PFC_GPSR4_D
 477
 478         write32 PFC_PMMR_A, PFC_PMMR_GPSR5
 479         write32 PFC_GPSR5_A, PFC_GPSR5_D
 480
 481         /* sleep 186A0 */
 482
 483         write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D
 484         write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D
 485         write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D
 486         write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D
 487         write32 GPIO4_INOUTSEL4_A,      GPIO4_INOUTSEL4_D
 488         write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D
 489
 490         write32 CCR_A,  CCR_D
 491
 492         stc sr, r0
 493         mov.l  SR_MASK_D, r1
 494         and r1, r0
 495         ldc r0, sr
 496
 497         rts
 498         nop
 499
 500         .align  2
 501
 502 PFC_PMMR_A:             .long   0xFFFC0000
 503
 504 /* MODESEL
 505  * 28: Select IEBUS Group B
 506  */
 507 PFC_MODESEL1_A: .long   0xFFFC004C
 508 PFC_MODESEL1_D: .long   0x10000000
 509 PFC_PMMR_MODESEL1:      .long   0xEFFFFFFF
 510
 511 /* MODESEL
 512  * 9: Select SCIF3 Group B
 513  * 7: Select SCIF2 Group B
 514  * 4: Select SCIF1 Group B
 515  */
 516 PFC_MODESEL2_A: .long   0xFFFC0050
 517 PFC_MODESEL2_D: .long   0x00000290
 518 PFC_PMMR_MODESEL2:      .long   0xFFFFFD6F
 519
 520 # Enable functios
 521 # SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A,
 522 # EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A,
 523 # SD1_CD_A, TX3_B, RX3_B, CS1, D15
 524 PFC_IPSR3_A:    .long   0xFFFC0028
 525 PFC_IPSR3_D:    .long   0x09209248
 526 PFC_PMMR_IPSR3: .long   0xF6DF6DB7
 527
 528 # Enable functios
 529 # RMII0_MDIO_A , RMII0_MDC_A,
 530 # RMII0_CRS_DV_A, RMII0_RX_ER_A,
 531 # RMII0_TXD_EN_A, MII0_RXD1_A
 532 PFC_IPSR4_A:    .long   0xFFFC002C
 533 PFC_IPSR4_D:    .long   0x0001B6DB
 534 PFC_PMMR_IPSR4: .long   0xFFFE4924
 535
 536 # Enable functios
 537 # DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B,
 538 # IETX_B, TX0_A, RMII0_TXD0_A,
 539 # RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1
 540 PFC_IPSR11_A:   .long   0xFFFC0048
 541 PFC_IPSR11_D:   .long   0x002C89B0
 542 PFC_PMMR_IPSR11:.long   0xFFD3764F
 543
 544 PFC_GPSR0_A:    .long   0xFFFC0004
 545 PFC_GPSR0_D:    .long   0xFFFFFFFF
 546 PFC_PMMR_GPSR0: .long   0x00000000
 547
 548 PFC_GPSR1_A:    .long   0xFFFC0008
 549 PFC_GPSR1_D:    .long   0x7FBF7FFF
 550 PFC_PMMR_GPSR1: .long   0x80408000
 551
 552 PFC_GPSR2_A:    .long   0xFFFC000C
 553 PFC_GPSR2_D:    .long   0xBFC07EDF
 554 PFC_PMMR_GPSR2: .long   0x403F8120
 555
 556 PFC_GPSR3_A:    .long   0xFFFC0010
 557 PFC_GPSR3_D:    .long   0xFFFFFFFF
 558 PFC_PMMR_GPSR3: .long   0x00000000
 559
 560 PFC_GPSR4_A:    .long   0xFFFC0014
 561 #if 0 /* orig */
 562 PFC_GPSR4_D:    .long   0xFFFFFFFF
 563 PFC_PMMR_GPSR4: .long   0x00000000
 564 #else
 565 PFC_GPSR4_D:    .long   0xFBFFFFFF
 566 PFC_PMMR_GPSR4: .long   0x04000000
 567 #endif
 568
 569 PFC_GPSR5_A:    .long   0xFFFC0018
 570 PFC_GPSR5_D:    .long   0x00000C01
 571 PFC_PMMR_GPSR5: .long   0xFFFFF3FE
 572
 573 I2C_ICCR2_A: .long      0xFFC70001
 574 I2C_ICCR2_D: .long      0x00
 575 I2C_ICCR2_D1: .long     0x20
 576
 577 GPIO2_INOUTSEL1_A:      .long   0xFFC41004
 578 GPIO2_INOUTSEL1_D:      .long   0x80408000
 579 GPIO1_OUTDT1_A:         .long   0xFFC41008      /* bit15: LED4, bit22: LED5 */
 580 GPIO1_OUTDT1_D:         .long   0x80408000
 581 GPIO2_INOUTSEL2_A:      .long   0xFFC42004
 582 GPIO2_INOUTSEL2_D:      .long   0x40000120
 583 GPIO2_OUTDT2_A:         .long   0xFFC42008
 584 GPIO2_OUTDT2_D:         .long   0x40000120
 585 GPIO4_INOUTSEL4_A:      .long   0xFFC44004
 586 GPIO4_INOUTSEL4_D:      .long   0x04000000
 587 GPIO4_OUTDT4_A:         .long   0xFFC44008
 588 GPIO4_OUTDT4_D:         .long   0x04000000
 589
 590 CCR_A:  .long   0xFF00001C
 591 CCR_D:  .long   0x0000090B
 592 SR_MASK_D:      .long   0xEFFFFF0F