git.sur5r.net Git - u-boot/blob - board/renesas/r0p7734/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   4  * Copyright (C) 2011 Renesas Solutions Corp.
   5  */
   6 #include <config.h>
   7 #include <asm/processor.h>
   8 #include <asm/macro.h>
   9
  10 #include <asm/processor.h>
  11
  12         .global lowlevel_init
  13
  14         .text
  15         .align  2
  16
  17 lowlevel_init:
  18
  19         /* WDT */
  20         write32 WDTCSR_A, WDTCSR_D
  21
  22         /* MMU */
  23         write32 MMUCR_A, MMUCR_D
  24
  25         write32 FRQCR2_A, FRQCR2_D
  26         write32 FRQCR0_A, FRQCR0_D
  27
  28         write32 CS0CTRL_A, CS0CTRL_D
  29         write32 CS1CTRL_A, CS1CTRL_D
  30         write32 CS0CTRL2_A, CS0CTRL2_D
  31
  32         write32 CSPWCR0_A, CSPWCR0_D
  33         write32 CSPWCR1_A, CSPWCR1_D
  34         write32 CS1GDST_A, CS1GDST_D
  35
  36         # clock mode check
  37         mov.l   MODEMR, r1
  38         mov.l   @r1, r0
  39         and             #6, r0 /* Check 1 and 2 bit.*/
  40         cmp/eq  #2, r0 /* 0x02 is 533Mhz mode */
  41         bt      init_lbsc_533
  42
  43 init_lbsc_400:
  44
  45         write32 CSWCR0_A, CSWCR0_D_400
  46         write32 CSWCR1_A, CSWCR1_D
  47
  48         bra     init_dbsc3_400_pad
  49         nop
  50
  51         .align 2
  52
  53 MODEMR:         .long   0xFFCC0020
  54 WDTCSR_A:       .long   0xFFCC0004
  55 WDTCSR_D:       .long   0xA5000000
  56 MMUCR_A:        .long   0xFF000010
  57 MMUCR_D:        .long   0x00000004
  58
  59 FRQCR2_A:       .long   0xFFC80008
  60 FRQCR2_D:       .long   0x00000000
  61 FRQCR0_A:       .long   0xFFC80000
  62 FRQCR0_D:       .long   0xCF000001
  63
  64 CS0CTRL_A:      .long   0xFF800200
  65 CS0CTRL_D:      .long   0x00000020
  66 CS1CTRL_A:      .long   0xFF800204
  67 CS1CTRL_D:      .long   0x00000020
  68
  69 CS0CTRL2_A:     .long   0xFF800220
  70 CS0CTRL2_D:     .long   0x00004000
  71
  72 CSPWCR0_A:      .long   0xFF800280
  73 CSPWCR0_D:      .long   0x00000000
  74 CSPWCR1_A:      .long   0xFF800284
  75 CSPWCR1_D:      .long   0x00000000
  76 CS1GDST_A:      .long   0xFF8002C0
  77 CS1GDST_D:      .long   0x00000011
  78
  79 init_lbsc_533:
  80
  81         write32 CSWCR0_A, CSWCR0_D_533
  82         write32 CSWCR1_A, CSWCR1_D
  83
  84         bra     init_dbsc3_533_pad
  85         nop
  86
  87         .align 2
  88
  89 CSWCR0_A:       .long   0xFF800230
  90 CSWCR0_D_533:   .long   0x01120104
  91 CSWCR0_D_400:   .long   0x02120114
  92 /* CSWCR0_D_400:        .long   0x01160116 */
  93 CSWCR1_A:       .long   0xFF800234
  94 CSWCR1_D:       .long   0x077F077F
  95 /* CSWCR1_D_400:        .long   0x00120012 */
  96
  97 init_dbsc3_400_pad:
  98
  99         write32 DBPDCNT3_A,     DBPDCNT3_D
 100         wait_timer      WAIT_200US_400
 101
 102         write32 DBPDCNT0_A,     DBPDCNT0_D_400
 103         write32 DBPDCNT3_A,     DBPDCNT3_D0
 104         write32 DBPDCNT1_A,     DBPDCNT1_D
 105
 106         write32 DBPDCNT3_A,     DBPDCNT3_D1
 107         wait_timer WAIT_32MCLK
 108
 109         write32 DBPDCNT3_A,     DBPDCNT3_D2
 110         wait_timer WAIT_100US_400
 111
 112         write32 DBPDCNT3_A,     DBPDCNT3_D3
 113         wait_timer WAIT_16MCLK
 114
 115         write32 DBPDCNT3_A,     DBPDCNT3_D4
 116         wait_timer WAIT_200US_400
 117
 118         write32 DBPDCNT3_A,     DBPDCNT3_D5
 119         wait_timer WAIT_1MCLK
 120
 121         write32 DBPDCNT3_A,     DBPDCNT3_D6
 122         wait_timer WAIT_10KMCLK
 123
 124         bra init_dbsc3_ctrl_400
 125         nop
 126
 127         .align 2
 128
 129 init_dbsc3_533_pad:
 130
 131         write32 DBPDCNT3_A,     DBPDCNT3_D
 132         wait_timer      WAIT_200US_533
 133
 134         write32 DBPDCNT0_A,     DBPDCNT0_D_533
 135         write32 DBPDCNT3_A,     DBPDCNT3_D0
 136         write32 DBPDCNT1_A,     DBPDCNT1_D
 137
 138         write32 DBPDCNT3_A,     DBPDCNT3_D1
 139         wait_timer WAIT_32MCLK
 140
 141         write32 DBPDCNT3_A,     DBPDCNT3_D2
 142         wait_timer WAIT_100US_533
 143
 144         write32 DBPDCNT3_A,     DBPDCNT3_D3
 145         wait_timer WAIT_16MCLK
 146
 147         write32 DBPDCNT3_A,     DBPDCNT3_D4
 148         wait_timer WAIT_200US_533
 149
 150         write32 DBPDCNT3_A,     DBPDCNT3_D5
 151         wait_timer WAIT_1MCLK
 152
 153         write32 DBPDCNT3_A,     DBPDCNT3_D6
 154         wait_timer      WAIT_10KMCLK
 155
 156         bra init_dbsc3_ctrl_533
 157         nop
 158
 159         .align 2
 160
 161 WAIT_200US_400: .long   40000
 162 WAIT_200US_533: .long   53300
 163 WAIT_100US_400: .long   20000
 164 WAIT_100US_533: .long   26650
 165 WAIT_32MCLK:    .long   32
 166 WAIT_16MCLK:    .long   16
 167 WAIT_1MCLK:             .long   1
 168 WAIT_10KMCLK:   .long   10000
 169
 170 DBPDCNT0_A:             .long   0xFE800200
 171 DBPDCNT0_D_533: .long   0x00010245
 172 DBPDCNT0_D_400: .long   0x00010235
 173 DBPDCNT1_A:             .long   0xFE800204
 174 DBPDCNT1_D:             .long   0x00000014
 175 DBPDCNT3_A:             .long   0xFE80020C
 176 DBPDCNT3_D:             .long   0x80000000
 177 DBPDCNT3_D0:    .long   0x800F0000
 178 DBPDCNT3_D1:    .long   0x800F1000
 179 DBPDCNT3_D2:    .long   0x820F1000
 180 DBPDCNT3_D3:    .long   0x860F1000
 181 DBPDCNT3_D4:    .long   0x870F1000
 182 DBPDCNT3_D5:    .long   0x870F3000
 183 DBPDCNT3_D6:    .long   0x870F7000
 184
 185 init_dbsc3_ctrl_400:
 186
 187         write32 DBKIND_A, DBKIND_D
 188         write32 DBCONF_A, DBCONF_D
 189
 190         write32 DBTR0_A,        DBTR0_D_400
 191         write32 DBTR1_A,        DBTR1_D_400
 192         write32 DBTR2_A,        DBTR2_D
 193         write32 DBTR3_A,        DBTR3_D_400
 194         write32 DBTR4_A,        DBTR4_D_400
 195         write32 DBTR5_A,        DBTR5_D_400
 196         write32 DBTR6_A,        DBTR6_D_400
 197         write32 DBTR7_A,        DBTR7_D
 198         write32 DBTR8_A,        DBTR8_D_400
 199         write32 DBTR9_A,        DBTR9_D
 200         write32 DBTR10_A,       DBTR10_D_400
 201         write32 DBTR11_A,       DBTR11_D
 202         write32 DBTR12_A,       DBTR12_D_400
 203         write32 DBTR13_A,       DBTR13_D_400
 204         write32 DBTR14_A,       DBTR14_D
 205         write32 DBTR15_A,       DBTR15_D
 206         write32 DBTR16_A,       DBTR16_D_400
 207         write32 DBTR17_A,       DBTR17_D_400
 208         write32 DBTR18_A,       DBTR18_D_400
 209
 210         write32 DBBL_A, DBBL_D
 211         write32 DBRNK0_A,       DBRNK0_D
 212
 213         write32 DBCMD_A,        DBCMD_D0_400
 214         write32 DBCMD_A,        DBCMD_D1
 215         write32 DBCMD_A,        DBCMD_D2
 216         write32 DBCMD_A,        DBCMD_D3
 217         write32 DBCMD_A,        DBCMD_D4
 218         write32 DBCMD_A,        DBCMD_D5_400
 219         write32 DBCMD_A,        DBCMD_D6
 220         write32 DBCMD_A,        DBCMD_D7
 221         write32 DBCMD_A,        DBCMD_D8
 222         write32 DBCMD_A,        DBCMD_D9_400
 223         write32 DBCMD_A,        DBCMD_D10
 224         write32 DBCMD_A,        DBCMD_D11
 225         write32 DBCMD_A,        DBCMD_D12
 226
 227         write32 DBBS0CNT1_A,    DBBS0CNT1_D
 228         write32 DBPDNCNF_A,             DBPDNCNF_D
 229
 230         write32 DBRFCNF0_A,     DBRFCNF0_D
 231         write32 DBRFCNF1_A,     DBRFCNF1_D_400
 232         write32 DBRFCNF2_A,     DBRFCNF2_D
 233         write32 DBRFEN_A,       DBRFEN_D
 234         write32 DBACEN_A,       DBACEN_D
 235         write32 DBACEN_A,       DBACEN_D
 236
 237         /* Dummy read */
 238         mov.l DBWAIT_A, r1
 239         synco
 240         mov.l @r1, r0
 241         synco
 242
 243         /* Dummy read */
 244         mov.l SDRAM_A, r1
 245         synco
 246         mov.l @r1, r0
 247         synco
 248
 249         /* need sleep 186A0 */
 250
 251         bra     init_pfc_sh7734
 252         nop
 253
 254         .align 2
 255
 256 init_dbsc3_ctrl_533:
 257
 258         write32 DBKIND_A, DBKIND_D
 259         write32 DBCONF_A, DBCONF_D
 260
 261         write32 DBTR0_A,        DBTR0_D_533
 262         write32 DBTR1_A,        DBTR1_D_533
 263         write32 DBTR2_A,        DBTR2_D
 264         write32 DBTR3_A,        DBTR3_D_533
 265         write32 DBTR4_A,        DBTR4_D_533
 266         write32 DBTR5_A,        DBTR5_D_533
 267         write32 DBTR6_A,        DBTR6_D_533
 268         write32 DBTR7_A,        DBTR7_D
 269         write32 DBTR8_A,        DBTR8_D_533
 270         write32 DBTR9_A,        DBTR9_D
 271         write32 DBTR10_A,       DBTR10_D_533
 272         write32 DBTR11_A,       DBTR11_D
 273         write32 DBTR12_A,       DBTR12_D_533
 274         write32 DBTR13_A,       DBTR13_D_533
 275         write32 DBTR14_A,       DBTR14_D
 276         write32 DBTR15_A,       DBTR15_D
 277         write32 DBTR16_A,       DBTR16_D_533
 278         write32 DBTR17_A,       DBTR17_D_533
 279         write32 DBTR18_A,       DBTR18_D_533
 280
 281         write32 DBBL_A, DBBL_D
 282         write32 DBRNK0_A,       DBRNK0_D
 283
 284         write32 DBCMD_A,        DBCMD_D0_533
 285         write32 DBCMD_A,        DBCMD_D1
 286         write32 DBCMD_A,        DBCMD_D2
 287         write32 DBCMD_A,        DBCMD_D3
 288         write32 DBCMD_A,        DBCMD_D4
 289         write32 DBCMD_A,        DBCMD_D5_533
 290         write32 DBCMD_A,        DBCMD_D6
 291         write32 DBCMD_A,        DBCMD_D7
 292         write32 DBCMD_A,        DBCMD_D8
 293         write32 DBCMD_A,        DBCMD_D9_533
 294         write32 DBCMD_A,        DBCMD_D10
 295         write32 DBCMD_A,        DBCMD_D11
 296         write32 DBCMD_A,        DBCMD_D12
 297
 298         write32 DBBS0CNT1_A,    DBBS0CNT1_D
 299         write32 DBPDNCNF_A,             DBPDNCNF_D
 300
 301         write32 DBRFCNF0_A,     DBRFCNF0_D
 302         write32 DBRFCNF1_A,     DBRFCNF1_D_533
 303         write32 DBRFCNF2_A,     DBRFCNF2_D
 304         write32 DBRFEN_A,       DBRFEN_D
 305         write32 DBACEN_A,       DBACEN_D
 306         write32 DBACEN_A,       DBACEN_D
 307
 308         /* Dummy read */
 309         mov.l DBWAIT_A, r1
 310         synco
 311         mov.l @r1, r0
 312         synco
 313
 314         /* Dummy read */
 315         mov.l SDRAM_A, r1
 316         synco
 317         mov.l @r1, r0
 318         synco
 319
 320         /* need sleep 186A0 */
 321
 322         bra     init_pfc_sh7734
 323         nop
 324
 325         .align 2
 326
 327 DBKIND_A:       .long   0xFE800020
 328 DBKIND_D:       .long   0x00000005
 329 DBCONF_A:       .long   0xFE800024
 330 DBCONF_D:       .long   0x0D030A01
 331
 332 DBTR0_A:        .long   0xFE800040
 333 DBTR0_D_533:.long       0x00000004
 334 DBTR0_D_400:.long       0x00000003
 335 DBTR1_A:        .long   0xFE800044
 336 DBTR1_D_533:.long       0x00000003
 337 DBTR1_D_400:.long       0x00000002
 338 DBTR2_A:        .long   0xFE800048
 339 DBTR2_D:        .long   0x00000000
 340 DBTR3_A:        .long   0xFE800050
 341 DBTR3_D_533:.long       0x00000004
 342 DBTR3_D_400:.long       0x00000003
 343
 344 DBTR4_A:        .long   0xFE800054
 345 DBTR4_D_533:.long       0x00050004
 346 DBTR4_D_400:.long       0x00050003
 347
 348 DBTR5_A:        .long   0xFE800058
 349 DBTR5_D_533:.long       0x0000000F
 350 DBTR5_D_400:.long       0x0000000B
 351
 352 DBTR6_A:        .long   0xFE80005C
 353 DBTR6_D_533:.long       0x0000000B
 354 DBTR6_D_400:.long       0x00000008
 355
 356 DBTR7_A:        .long   0xFE800060
 357 DBTR7_D:        .long   0x00000002 /* common value */
 358
 359 DBTR8_A:        .long   0xFE800064
 360 DBTR8_D_533:.long       0x0000000D
 361 DBTR8_D_400:.long       0x0000000A
 362
 363 DBTR9_A:        .long   0xFE800068
 364 DBTR9_D:        .long   0x00000002 /* common value */
 365
 366 DBTR10_A:       .long   0xFE80006C
 367 DBTR10_D_533:.long      0x00000004
 368 DBTR10_D_400:.long      0x00000003
 369
 370 DBTR11_A:       .long   0xFE800070
 371 DBTR11_D:       .long   0x00000008 /* common value */
 372
 373 DBTR12_A:       .long   0xFE800074
 374 DBTR12_D_533:.long      0x00000009
 375 DBTR12_D_400:.long      0x00000008
 376
 377 DBTR13_A:       .long   0xFE800078
 378 DBTR13_D_533:.long      0x00000022
 379 DBTR13_D_400:.long      0x0000001A
 380
 381 DBTR14_A:       .long   0xFE80007C
 382 DBTR14_D:       .long   0x00070002 /* common value */
 383
 384 DBTR15_A:       .long   0xFE800080
 385 DBTR15_D:       .long   0x00000003 /* common value */
 386
 387 DBTR16_A:       .long   0xFE800084
 388 DBTR16_D_533:.long      0x120A1001
 389 DBTR16_D_400:.long      0x12091001
 390
 391 DBTR17_A:       .long   0xFE800088
 392 DBTR17_D_533:.long      0x00040000
 393 DBTR17_D_400:.long      0x00030000
 394
 395 DBTR18_A:       .long   0xFE80008C
 396 DBTR18_D_533:.long      0x02010200
 397 DBTR18_D_400:.long      0x02000207
 398
 399 DBBL_A: .long   0xFE8000B0
 400 DBBL_D: .long   0x00000000
 401
 402 DBRNK0_A:               .long   0xFE800100
 403 DBRNK0_D:               .long   0x00000001
 404
 405 DBCMD_A:                .long   0xFE800018
 406 DBCMD_D0_533:   .long   0x1100006B
 407 DBCMD_D0_400:   .long   0x11000050
 408 DBCMD_D1:               .long   0x0B000000 /* common value */
 409 DBCMD_D2:               .long   0x2A004000 /* common value */
 410 DBCMD_D3:               .long   0x2B006000 /* common value */
 411 DBCMD_D4:               .long   0x29002004 /* common value */
 412 DBCMD_D5_533:   .long   0x28000743
 413 DBCMD_D5_400:   .long   0x28000533
 414 DBCMD_D6:               .long   0x0B000000 /* common value */
 415 DBCMD_D7:               .long   0x0C000000 /* common value */
 416 DBCMD_D8:               .long   0x0C000000 /* common value */
 417 DBCMD_D9_533:   .long   0x28000643
 418 DBCMD_D9_400:   .long   0x28000433
 419 DBCMD_D10:              .long   0x000000C8 /* common value */
 420 DBCMD_D11:              .long   0x29002384 /* common value */
 421 DBCMD_D12:              .long   0x29002004 /* common value */
 422
 423 DBBS0CNT1_A:    .long   0xFE800304
 424 DBBS0CNT1_D:    .long   0x00000000
 425 DBPDNCNF_A:             .long   0xFE800180
 426 DBPDNCNF_D:             .long   0x00000200
 427
 428 DBRFCNF0_A:             .long   0xFE8000E0
 429 DBRFCNF0_D:             .long   0x000001FF
 430 DBRFCNF1_A:             .long   0xFE8000E4
 431 DBRFCNF1_D_533: .long   0x00000805
 432 DBRFCNF1_D_400: .long   0x00000618
 433
 434 DBRFCNF2_A:             .long   0xFE8000E8
 435 DBRFCNF2_D:             .long   0x00000000
 436
 437 DBRFEN_A:               .long   0xFE800014
 438 DBRFEN_D:               .long   0x00000001
 439
 440 DBACEN_A:               .long   0xFE800010
 441 DBACEN_D:               .long   0x00000001
 442
 443 DBWAIT_A:               .long   0xFE80001C
 444 SDRAM_A:                .long   0x0C000000
 445
 446 init_pfc_sh7734:
 447         write32 PFC_PMMR_A, PFC_PMMR_MODESEL1
 448         write32 PFC_MODESEL1_A, PFC_MODESEL1_D
 449
 450         write32 PFC_PMMR_A, PFC_PMMR_MODESEL2
 451         write32 PFC_MODESEL2_A, PFC_MODESEL2_D
 452
 453         write32 PFC_PMMR_A, PFC_PMMR_IPSR3
 454         write32 PFC_IPSR3_A, PFC_IPSR3_D
 455
 456         write32 PFC_PMMR_A, PFC_PMMR_IPSR4
 457         write32 PFC_IPSR4_A, PFC_IPSR4_D
 458
 459         write32 PFC_PMMR_A, PFC_PMMR_IPSR11
 460         write32 PFC_IPSR11_A, PFC_IPSR11_D
 461
 462         write32 PFC_PMMR_A, PFC_PMMR_GPSR0
 463         write32 PFC_GPSR0_A, PFC_GPSR0_D
 464
 465         write32 PFC_PMMR_A, PFC_PMMR_GPSR1
 466         write32 PFC_GPSR1_A, PFC_GPSR1_D
 467
 468         write32 PFC_PMMR_A, PFC_PMMR_GPSR2
 469         write32 PFC_GPSR2_A, PFC_GPSR2_D
 470
 471         write32 PFC_PMMR_A, PFC_PMMR_GPSR3
 472         write32 PFC_GPSR3_A, PFC_GPSR3_D
 473
 474         write32 PFC_PMMR_A, PFC_PMMR_GPSR4
 475         write32 PFC_GPSR4_A, PFC_GPSR4_D
 476
 477         write32 PFC_PMMR_A, PFC_PMMR_GPSR5
 478         write32 PFC_GPSR5_A, PFC_GPSR5_D
 479
 480         /* sleep 186A0 */
 481
 482         write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D
 483         write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D
 484         write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D
 485         write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D
 486         write32 GPIO4_INOUTSEL4_A,      GPIO4_INOUTSEL4_D
 487         write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D
 488
 489         write32 CCR_A,  CCR_D
 490
 491         stc sr, r0
 492         mov.l  SR_MASK_D, r1
 493         and r1, r0
 494         ldc r0, sr
 495
 496         rts
 497         nop
 498
 499         .align  2
 500
 501 PFC_PMMR_A:             .long   0xFFFC0000
 502
 503 /* MODESEL
 504  * 28: Select IEBUS Group B
 505  */
 506 PFC_MODESEL1_A: .long   0xFFFC004C
 507 PFC_MODESEL1_D: .long   0x10000000
 508 PFC_PMMR_MODESEL1:      .long   0xEFFFFFFF
 509
 510 /* MODESEL
 511  * 9: Select SCIF3 Group B
 512  * 7: Select SCIF2 Group B
 513  * 4: Select SCIF1 Group B
 514  */
 515 PFC_MODESEL2_A: .long   0xFFFC0050
 516 PFC_MODESEL2_D: .long   0x00000290
 517 PFC_PMMR_MODESEL2:      .long   0xFFFFFD6F
 518
 519 # Enable functios
 520 # SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A,
 521 # EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A,
 522 # SD1_CD_A, TX3_B, RX3_B, CS1, D15
 523 PFC_IPSR3_A:    .long   0xFFFC0028
 524 PFC_IPSR3_D:    .long   0x09209248
 525 PFC_PMMR_IPSR3: .long   0xF6DF6DB7
 526
 527 # Enable functios
 528 # RMII0_MDIO_A , RMII0_MDC_A,
 529 # RMII0_CRS_DV_A, RMII0_RX_ER_A,
 530 # RMII0_TXD_EN_A, MII0_RXD1_A
 531 PFC_IPSR4_A:    .long   0xFFFC002C
 532 PFC_IPSR4_D:    .long   0x0001B6DB
 533 PFC_PMMR_IPSR4: .long   0xFFFE4924
 534
 535 # Enable functios
 536 # DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B,
 537 # IETX_B, TX0_A, RMII0_TXD0_A,
 538 # RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1
 539 PFC_IPSR11_A:   .long   0xFFFC0048
 540 PFC_IPSR11_D:   .long   0x002C89B0
 541 PFC_PMMR_IPSR11:.long   0xFFD3764F
 542
 543 PFC_GPSR0_A:    .long   0xFFFC0004
 544 PFC_GPSR0_D:    .long   0xFFFFFFFF
 545 PFC_PMMR_GPSR0: .long   0x00000000
 546
 547 PFC_GPSR1_A:    .long   0xFFFC0008
 548 PFC_GPSR1_D:    .long   0x7FBF7FFF
 549 PFC_PMMR_GPSR1: .long   0x80408000
 550
 551 PFC_GPSR2_A:    .long   0xFFFC000C
 552 PFC_GPSR2_D:    .long   0xBFC07EDF
 553 PFC_PMMR_GPSR2: .long   0x403F8120
 554
 555 PFC_GPSR3_A:    .long   0xFFFC0010
 556 PFC_GPSR3_D:    .long   0xFFFFFFFF
 557 PFC_PMMR_GPSR3: .long   0x00000000
 558
 559 PFC_GPSR4_A:    .long   0xFFFC0014
 560 #if 0 /* orig */
 561 PFC_GPSR4_D:    .long   0xFFFFFFFF
 562 PFC_PMMR_GPSR4: .long   0x00000000
 563 #else
 564 PFC_GPSR4_D:    .long   0xFBFFFFFF
 565 PFC_PMMR_GPSR4: .long   0x04000000
 566 #endif
 567
 568 PFC_GPSR5_A:    .long   0xFFFC0018
 569 PFC_GPSR5_D:    .long   0x00000C01
 570 PFC_PMMR_GPSR5: .long   0xFFFFF3FE
 571
 572 I2C_ICCR2_A: .long      0xFFC70001
 573 I2C_ICCR2_D: .long      0x00
 574 I2C_ICCR2_D1: .long     0x20
 575
 576 GPIO2_INOUTSEL1_A:      .long   0xFFC41004
 577 GPIO2_INOUTSEL1_D:      .long   0x80408000
 578 GPIO1_OUTDT1_A:         .long   0xFFC41008      /* bit15: LED4, bit22: LED5 */
 579 GPIO1_OUTDT1_D:         .long   0x80408000
 580 GPIO2_INOUTSEL2_A:      .long   0xFFC42004
 581 GPIO2_INOUTSEL2_D:      .long   0x40000120
 582 GPIO2_OUTDT2_A:         .long   0xFFC42008
 583 GPIO2_OUTDT2_D:         .long   0x40000120
 584 GPIO4_INOUTSEL4_A:      .long   0xFFC44004
 585 GPIO4_INOUTSEL4_D:      .long   0x04000000
 586 GPIO4_OUTDT4_A:         .long   0xFFC44008
 587 GPIO4_OUTDT4_D:         .long   0x04000000
 588
 589 CCR_A:  .long   0xFF00001C
 590 CCR_D:  .long   0x0000090B
 591 SR_MASK_D:      .long   0xEFFFFF0F