2 * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
3 * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
4 * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
10 #include <asm/processor.h>
86 /* Wait DRAM refresh 30 times */
115 CCR_A: .long CCR /* Cache Control Register */
116 CCR_D_D: .long 0x0808 /* Flush the cache, disable */
117 CCR_D_E: .long 0x8000090B
119 FRQCR_A: .long FRQCR /* FRQCR Address */
120 FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
121 BCR1_A: .long BCR1 /* BCR1 Address */
122 BCR1_D: .long 0x00180008
123 BCR2_A: .long BCR2 /* BCR2 Address */
125 BCR3_A: .long BCR3 /* BCR3 Address */
127 BCR4_A: .long BCR4 /* BCR4 Address */
128 BCR4_D: .long 0x00000010
129 WCR1_A: .long WCR1 /* WCR1 Address */
130 WCR1_D: .long 0x33343333
131 WCR2_A: .long WCR2 /* WCR2 Address */
132 WCR2_D: .long 0xcff86fbf
133 WCR3_A: .long WCR3 /* WCR3 Address */
134 WCR3_D: .long 0x07777707
135 LED_A: .long 0x04000036 /* LED Address */
136 RTCNT_A: .long RTCNT /* RTCNT Address */
137 RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
138 RTCOR_A: .long RTCOR /* RTCOR Address */
139 RTCOR_D: .long 0xA534 /* RTCOR Write Code */
140 RTCSR_A: .long RTCSR /* RTCSR Address */
141 RTCSR_D: .long 0xA510 /* RTCSR Write Code */
142 SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
144 MCR_A: .long MCR /* MCR Address */
145 MCR_D1: .long 0x081901F4 /* MRSET:'0' */
146 MCR_D2: .long 0x481901F4 /* MRSET:'1' */
147 RFCR_A: .long RFCR /* RFCR Address */
148 RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
149 PCR_A: .long PCR /* PCR Address */
151 MMUCR_A: .long MMUCR /* MMUCCR Address */
152 MMUCR_D: .long 0x00000000 /* MMUCCR Data */
153 IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
154 IRLMASK_D: .long 0x00000000 /* IRLMASK Data */