2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
4 * u-boot/board/r7780mp/lowlevel_init.S
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
27 * Board specific low level init code, called _very_ early in the
28 * startup sequence. Relocation to SDRAM has not happened yet, no
29 * stack is available, bss section has not been initialised, etc.
31 * (Note: As no stack is available, no subroutines can be called...).
41 mov.l CCR_A, r1 /* Address of Cache Control Register */
42 mov.l CCR_D, r0 /* Instruction Cache Invalidate */
45 mov.l FRQCR_A, r1 /* Frequency control register */
49 /* pin_multi_setting */
51 mov.l BBG_PMMR_D_PMSR1, r0
59 mov.l BBG_PMMR_D_PMSR2, r0
67 mov.l BBG_PMMR_D_PMSR3, r0
75 mov.l BBG_PMMR_D_PMSR4, r0
83 mov.l BBG_PMMR_D_PMSRG, r0
325 RWTCSR_D_1: .word 0xA507
326 RWTCSR_D_2: .word 0xA507
327 RWTCNT_D: .word 0x5A00
330 BBG_PMMR_A: .long 0xFF800010
331 BBG_PMSR1_A: .long 0xFF800014
332 BBG_PMSR2_A: .long 0xFF800018
333 BBG_PMSR3_A: .long 0xFF80001C
334 BBG_PMSR4_A: .long 0xFF800020
335 BBG_PMSRG_A: .long 0xFF800024
337 BBG_PMMR_D_PMSR1: .long 0xffffbffd
338 BBG_PMSR1_D: .long 0x00004002
339 BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
340 BBG_PMSR2_D: .long 0x03de5800
341 BBG_PMMR_D_PMSR3: .long 0xfffffff8
342 BBG_PMSR3_D: .long 0x00000007
343 BBG_PMMR_D_PMSR4: .long 0xdffdfff9
344 BBG_PMSR4_D: .long 0x20020006
345 BBG_PMMR_D_PMSRG: .long 0xffffffff
346 BBG_PMSRG_D: .long 0x00000000
349 DLLCSR_A: .long 0xffc40010
350 FRQCR_D: .long 0x40233035
351 DLLCSR_D: .long 0x00000000
363 EMRS_A: .long 0xFEC02000
364 MRS1_A: .long 0xFEC00B08
365 MRS2_A: .long 0xFEC00308
367 MIM_U_D: .long 0x00004000
368 MIM_L_D0: .long 0x03e80009
369 MIM_L_D1: .long 0x03e80209
376 STR_L_D: .long 0x000f0000
377 SDR_L_D: .long 0x00000400
382 /* Cache Controller */
385 RWTCNT_A: .long WTCNT
387 CCR_D: .long 0x0000090b
388 CCR_D_2: .long 0x00000103
389 MMUCR_D: .long 0x00000004
390 MSTPCR0_D: .long 0x00001001
391 MSTPCR2_D: .long 0xffffffff
393 /* local Bus State Controller */
394 MMSELR_A: .long MMSELR
396 CS0BCR_A: .long CS0BCR
397 CS1BCR_A: .long CS1BCR
398 CS2BCR_A: .long CS2BCR
399 CS4BCR_A: .long CS4BCR
400 CS5BCR_A: .long CS5BCR
401 CS6BCR_A: .long CS6BCR
402 CS0WCR_A: .long CS0WCR
403 CS1WCR_A: .long CS1WCR
404 CS2WCR_A: .long CS2WCR
405 CS4WCR_A: .long CS4WCR
406 CS5WCR_A: .long CS5WCR
407 CS6WCR_A: .long CS6WCR
408 CS5PCR_A: .long CS5PCR
409 CS6PCR_A: .long CS6PCR
411 MMSELR_D: .long 0xA5A50003
412 BCR_D: .long 0x00000000
413 CS0BCR_D: .long 0x77777770
414 CS1BCR_D: .long 0x77777670
415 CS2BCR_D: .long 0x77777770
416 CS4BCR_D: .long 0x77777770
417 CS5BCR_D: .long 0x77777670
418 CS6BCR_D: .long 0x77777770
419 CS0WCR_D: .long 0x00020006
420 CS1WCR_D: .long 0x00232304
421 CS2WCR_D: .long 0x7777770F
422 CS4WCR_D: .long 0x7777770F
423 CS5WCR_D: .long 0x00101006
424 CS6WCR_D: .long 0x77777703
425 CS5PCR_D: .long 0x77000000
426 CS6PCR_D: .long 0x77000000
428 REPEAT0_R3: .long 0x00002000
429 REPEAT0_R1: .long 0x0000200