2 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
3 * Copyright (C) 2012 Phil Edworthy
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
7 * Based on board/renesas/rsk7264/lowlevel_init.S
9 * This file is released under the terms of GPL v2 and any later version.
10 * See the file COPYING in the root directory of the source tree for details.
15 #include <asm/processor.h>
16 #include <asm/macro.h>
24 /* Flush and enable caches (data cache in write-through mode) */
25 write32 CCR1_A ,CCR1_D
28 write16 WTCSR_A, WTCSR_D
29 write16 WTCNT_A, WTCNT_D
31 /* Disable Register Bank interrupts */
32 write16 IBNR_A, IBNR_D
34 /* Set clocks based on 13.225MHz xtal */
35 write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
37 /* Enable all peripherals */
38 write8 STBCR3_A, STBCR3_D
39 write8 STBCR4_A, STBCR4_D
40 write8 STBCR5_A, STBCR5_D
41 write8 STBCR6_A, STBCR6_D
42 write8 STBCR7_A, STBCR7_D
43 write8 STBCR8_A, STBCR8_D
44 write8 STBCR9_A, STBCR9_D
45 write8 STBCR10_A, STBCR10_D
48 write16 PJCR3_A, PJCR3_D /* TXD7 */
49 write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
51 /* Configure bus (CS0) */
52 write16 PFCR3_A, PFCR3_D /* A24 */
53 write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
54 write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
55 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
56 write32 CS0WCR_A, CS0WCR_D
57 write32 CS0BCR_A, CS0BCR_D
59 /* Configure SDRAM (CS3) */
60 write16 PCCR2_A, PCCR2_D /* CS3# */
61 write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
62 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
63 write32 CS3BCR_A, CS3BCR_D
64 write32 CS3WCR_A, CS3WCR_D
65 write32 SDCR_A, SDCR_D
66 write32 RTCOR_A, RTCOR_D
67 write32 RTCSR_A, RTCSR_D
69 /* Configure ethernet (CS1) */
70 write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
71 write16 PHCR0_A, PHCR0_D
72 write16 PFCR2_A, PFCR2_D /* CS1# */
73 write32 CS1BCR_A, CS1BCR_D /* Big endian */
74 write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
75 write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
76 write16 PJIOR1_A, PJIOR1_D
97 CCR1_D: .long 0x0000090B
99 STBCR3_A: .long 0xFFFE0408
100 STBCR4_A: .long 0xFFFE040C
101 STBCR5_A: .long 0xFFFE0410
102 STBCR6_A: .long 0xFFFE0414
103 STBCR7_A: .long 0xFFFE0418
104 STBCR8_A: .long 0xFFFE041C
105 STBCR9_A: .long 0xFFFE0440
106 STBCR10_A: .long 0xFFFE0444
107 STBCR3_D: .long 0x0000001A
108 STBCR4_D: .long 0x00000000
109 STBCR5_D: .long 0x00000000
110 STBCR6_D: .long 0x00000000
111 STBCR7_D: .long 0x00000012
112 STBCR8_D: .long 0x00000009
113 STBCR9_D: .long 0x00000000
114 STBCR10_D: .long 0x00000010
116 WTCSR_A: .long 0xFFFE0000
117 WTCNT_A: .long 0xFFFE0002
118 WTCSR_D: .word 0xA518
119 WTCNT_D: .word 0x5A00
121 IBNR_A: .long 0xFFFE080E
124 FRQCR_A: .long 0xFFFE0010
125 FRQCR_D: .word 0x0015
128 PJCR3_A: .long 0xFFFE3908
129 PJCR3_D: .word 0x5000
131 PECR1_A: .long 0xFFFE388C
132 PECR1_D: .word 0x2011
135 PFCR3_A: .long 0xFFFE38A8
136 PFCR2_A: .long 0xFFFE38AA
137 PBCR5_A: .long 0xFFFE3824
138 PFCR3_D: .word 0x0010
139 PFCR2_D: .word 0x0101
140 PBCR5_D: .word 0x0111
142 CS0WCR_A: .long 0xFFFC0028
143 CS0WCR_D: .long 0x00000341
144 CS0BCR_A: .long 0xFFFC0004
145 CS0BCR_D: .long 0x00000400
147 PCCR2_A: .long 0xFFFE384A
148 PCCR1_A: .long 0xFFFE384C
149 PCCR0_A: .long 0xFFFE384E
150 PCCR2_D: .word 0x0001
151 PCCR1_D: .word 0x1111
152 PCCR0_D: .word 0x1111
154 CS3BCR_A: .long 0xFFFC0010
155 CS3BCR_D: .long 0x00004400
156 CS3WCR_A: .long 0xFFFC0034
157 CS3WCR_D: .long 0x00004912
158 SDCR_A: .long 0xFFFC004C
159 SDCR_D: .long 0x00000811
160 RTCOR_A: .long 0xFFFC0058
161 RTCOR_D: .long 0xA55A0035
162 RTCSR_A: .long 0xFFFC0050
163 RTCSR_D: .long 0xA55A0010
165 SDRAM_MODE: .long 0xFFFC5460
166 REPEAT_D: .long 0x000033F1
168 PHCR1_A: .long 0xFFFE38EC
169 PHCR0_A: .long 0xFFFE38EE
170 PHCR1_D: .word 0x2222
171 PHCR0_D: .word 0x2222
173 CS1BCR_A: .long 0xFFFC0008
174 CS1BCR_D: .long 0x00000400
175 CS1WCR_A: .long 0xFFFC002C
176 CS1WCR_D: .long 0x00000080
177 PJDR1_A: .long 0xFFFE3914
178 PJDR1_D: .word 0x0000
180 PJIOR1_A: .long 0xFFFE3910
181 PJIOR1_D: .word 0x8000