2 * Copyright (C) 2012 Renesas Solutions Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/processor.h>
23 #include <asm/macro.h>
25 .macro or32, addr, data
39 .section .spiboot1.text
43 /*------- GPIO -------*/
44 write16 PDCR_A, PDCR_D ! SPI0
45 write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
46 write16 PJCR_A, PJCR_D ! SCIF4
47 write16 PTCR_A, PTCR_D ! STATUS
48 write16 PSEL1_A, PSEL1_D ! SPI0
49 write16 PSEL2_A, PSEL2_D ! SPI0
50 write16 PSEL5_A, PSEL5_D ! STATUS
57 /*------- GPIO -------*/
58 PDCR_A: .long 0xffec0006
59 PGCR_A: .long 0xffec000c
60 PJCR_A: .long 0xffec0012
61 PTCR_A: .long 0xffec0026
62 PSEL1_A: .long 0xffec0072
63 PSEL2_A: .long 0xffec0074
64 PSEL5_A: .long 0xffec007a
88 /* If CPU runs on SDRAM (PC=0x5???????) or not. */
89 PC_MASK: .long 0x20000000
96 mov.l EXPEVT_POWER_ON_RESET, r1
101 * If EXPEVT value is manual reset or tlb multipul-hit,
102 * initialization of DDR3IF is not necessary.
108 /*------- Reset -------*/
109 write32 MRSTCR0_A, MRSTCR0_D
110 write32 MRSTCR1_A, MRSTCR1_D
119 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
120 * initialization of DDR3-SDRAM.
126 /*------- DDR3IF -------*/
127 /* oscillation stabilization time */
128 wait_timer WAIT_OSC_TIME
131 write32 DBCMD_A, DBCMD_RSTL_VAL
135 write32 DBCMD_A, DBCMD_PDEN_VAL
138 write32 DBKIND_A, DBKIND_D
141 write32 DBCONF_A, DBCONF_D
142 write32 DBTR0_A, DBTR0_D
143 write32 DBTR1_A, DBTR1_D
144 write32 DBTR2_A, DBTR2_D
145 write32 DBTR3_A, DBTR3_D
146 write32 DBTR4_A, DBTR4_D
147 write32 DBTR5_A, DBTR5_D
148 write32 DBTR6_A, DBTR6_D
149 write32 DBTR7_A, DBTR7_D
150 write32 DBTR8_A, DBTR8_D
151 write32 DBTR9_A, DBTR9_D
152 write32 DBTR10_A, DBTR10_D
153 write32 DBTR11_A, DBTR11_D
154 write32 DBTR12_A, DBTR12_D
155 write32 DBTR13_A, DBTR13_D
156 write32 DBTR14_A, DBTR14_D
157 write32 DBTR15_A, DBTR15_D
158 write32 DBTR16_A, DBTR16_D
159 write32 DBTR17_A, DBTR17_D
160 write32 DBTR18_A, DBTR18_D
161 write32 DBTR19_A, DBTR19_D
162 write32 DBRNK0_A, DBRNK0_D
165 write32 DBPDCNT3_A, DBPDCNT3_D
168 write32 DBPDCNT1_A, DBPDCNT1_D
169 write32 DBPDCNT2_A, DBPDCNT2_D
170 write32 DBPDLCK_A, DBPDLCK_D
171 write32 DBPDRGA_A, DBPDRGA_D
172 write32 DBPDRGD_A, DBPDRGD_D
178 write32 DBPDCNT0_A, DBPDCNT0_D
185 write32 DBCMD_A, DBCMD_WAIT_VAL
189 write32 DBCMD_A, DBCMD_RSTH_VAL
193 write32 DBCMD_A, DBCMD_WAIT_VAL
194 write32 DBCMD_A, DBCMD_WAIT_VAL
195 write32 DBCMD_A, DBCMD_WAIT_VAL
196 write32 DBCMD_A, DBCMD_WAIT_VAL
199 write32 DBCMD_A, DBCMD_PDXT_VAL
202 write32 DBCMD_A, DBCMD_MRS2_VAL
205 write32 DBCMD_A, DBCMD_MRS3_VAL
208 write32 DBCMD_A, DBCMD_MRS1_VAL
211 write32 DBCMD_A, DBCMD_MRS0_VAL
214 write32 DBCMD_A, DBCMD_ZQCL_VAL
216 write32 DBCMD_A, DBCMD_REF_VAL
217 write32 DBCMD_A, DBCMD_REF_VAL
221 write32 DBADJ0_A, DBADJ0_D
222 write32 DBADJ1_A, DBADJ1_D
223 write32 DBADJ2_A, DBADJ2_D
226 write32 DBRFCNF0_A, DBRFCNF0_D
227 write32 DBRFCNF1_A, DBRFCNF1_D
228 write32 DBRFCNF2_A, DBRFCNF2_D
231 write32 DBCALCNF_A, DBCALCNF_D
234 write32 DBRFEN_A, DBRFEN_D
235 write32 DBCMD_A, DBCMD_SRXT_VAL
238 write32 DBACEN_A, DBACEN_D
248 EXPEVT_A: .long 0xff000024
249 EXPEVT_POWER_ON_RESET: .long 0x00000000
251 /*------- Reset -------*/
252 MRSTCR0_A: .long 0xffd50030
253 MRSTCR0_D: .long 0xfe1ffe7f
254 MRSTCR1_A: .long 0xffd50034
255 MRSTCR1_D: .long 0xfff3ffff
257 /*------- DDR3IF -------*/
258 DBCMD_A: .long 0xfe800018
259 DBKIND_A: .long 0xfe800020
260 DBCONF_A: .long 0xfe800024
261 DBTR0_A: .long 0xfe800040
262 DBTR1_A: .long 0xfe800044
263 DBTR2_A: .long 0xfe800048
264 DBTR3_A: .long 0xfe800050
265 DBTR4_A: .long 0xfe800054
266 DBTR5_A: .long 0xfe800058
267 DBTR6_A: .long 0xfe80005c
268 DBTR7_A: .long 0xfe800060
269 DBTR8_A: .long 0xfe800064
270 DBTR9_A: .long 0xfe800068
271 DBTR10_A: .long 0xfe80006c
272 DBTR11_A: .long 0xfe800070
273 DBTR12_A: .long 0xfe800074
274 DBTR13_A: .long 0xfe800078
275 DBTR14_A: .long 0xfe80007c
276 DBTR15_A: .long 0xfe800080
277 DBTR16_A: .long 0xfe800084
278 DBTR17_A: .long 0xfe800088
279 DBTR18_A: .long 0xfe80008c
280 DBTR19_A: .long 0xfe800090
281 DBRNK0_A: .long 0xfe800100
282 DBPDCNT0_A: .long 0xfe800200
283 DBPDCNT1_A: .long 0xfe800204
284 DBPDCNT2_A: .long 0xfe800208
285 DBPDCNT3_A: .long 0xfe80020c
286 DBPDLCK_A: .long 0xfe800280
287 DBPDRGA_A: .long 0xfe800290
288 DBPDRGD_A: .long 0xfe8002a0
289 DBADJ0_A: .long 0xfe8000c0
290 DBADJ1_A: .long 0xfe8000c4
291 DBADJ2_A: .long 0xfe8000c8
292 DBRFCNF0_A: .long 0xfe8000e0
293 DBRFCNF1_A: .long 0xfe8000e4
294 DBRFCNF2_A: .long 0xfe8000e8
295 DBCALCNF_A: .long 0xfe8000f4
296 DBRFEN_A: .long 0xfe800014
297 DBACEN_A: .long 0xfe800010
298 DBWAIT_A: .long 0xfe80001c
300 WAIT_OSC_TIME: .long 6000
301 WAIT_30US: .long 13333
303 DBCMD_RSTL_VAL: .long 0x20000000
304 DBCMD_PDEN_VAL: .long 0x1000d73c
305 DBCMD_WAIT_VAL: .long 0x0000d73c
306 DBCMD_RSTH_VAL: .long 0x2100d73c
307 DBCMD_PDXT_VAL: .long 0x110000c8
308 DBCMD_MRS0_VAL: .long 0x28000930
309 DBCMD_MRS1_VAL: .long 0x29000004
310 DBCMD_MRS2_VAL: .long 0x2a000008
311 DBCMD_MRS3_VAL: .long 0x2b000000
312 DBCMD_ZQCL_VAL: .long 0x03000200
313 DBCMD_REF_VAL: .long 0x0c000000
314 DBCMD_SRXT_VAL: .long 0x19000000
315 DBKIND_D: .long 0x00000007
316 DBCONF_D: .long 0x0f030a01
317 DBTR0_D: .long 0x00000007
318 DBTR1_D: .long 0x00000006
319 DBTR2_D: .long 0x00000000
320 DBTR3_D: .long 0x00000007
321 DBTR4_D: .long 0x00070007
322 DBTR5_D: .long 0x0000001b
323 DBTR6_D: .long 0x00000014
324 DBTR7_D: .long 0x00000005
325 DBTR8_D: .long 0x00000015
326 DBTR9_D: .long 0x00000006
327 DBTR10_D: .long 0x00000008
328 DBTR11_D: .long 0x00000007
329 DBTR12_D: .long 0x0000000e
330 DBTR13_D: .long 0x00000056
331 DBTR14_D: .long 0x00000006
332 DBTR15_D: .long 0x00000004
333 DBTR16_D: .long 0x00150002
334 DBTR17_D: .long 0x000c0017
335 DBTR18_D: .long 0x00000200
336 DBTR19_D: .long 0x00000040
337 DBRNK0_D: .long 0x00000001
338 DBPDCNT0_D: .long 0x00000001
339 DBPDCNT1_D: .long 0x00000001
340 DBPDCNT2_D: .long 0x00000000
341 DBPDCNT3_D: .long 0x00004010
342 DBPDLCK_D: .long 0x0000a55a
343 DBPDRGA_D: .long 0x00000028
344 DBPDRGD_D: .long 0x00017100
346 DBADJ0_D: .long 0x00000000
347 DBADJ1_D: .long 0x00000000
348 DBADJ2_D: .long 0x18061806
349 DBRFCNF0_D: .long 0x000001ff
350 DBRFCNF1_D: .long 0x08001000
351 DBRFCNF2_D: .long 0x00000000
352 DBCALCNF_D: .long 0x0000ffff
353 DBRFEN_D: .long 0x00000001
354 DBACEN_D: .long 0x00000001
358 #if defined(CONFIG_SH_32BIT)
359 /*------- set PMB -------*/
360 write32 PASCR_A, PASCR_29BIT_D
361 write32 MMUCR_A, MMUCR_D
363 /*****************************************************************
364 * ent virt phys v sz c wt
365 * 0 0xa0000000 0x00000000 1 128M 0 1
366 * 1 0xa8000000 0x48000000 1 128M 0 1
367 * 5 0x88000000 0x48000000 1 128M 1 1
369 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
370 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
371 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
372 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
373 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
374 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
376 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
377 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
378 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
379 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
380 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
381 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
382 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
383 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
384 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
385 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
386 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
387 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
388 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
390 write32 PASCR_A, PASCR_INIT
393 #endif /* if defined(CONFIG_SH_32BIT) */
396 /* CPU is running on ILRAM? */
401 mov.l _stack_ilram, r15
402 mov.l _spiboot_main, r0
407 _spiboot_main: .long (spiboot_main - (100b + 4))
408 _stack_ilram: .long 0xe5204000
418 #if defined(CONFIG_SH_32BIT)
419 /*------- set PMB -------*/
420 PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
421 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
422 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
423 PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
424 PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
425 PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
426 PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
427 PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
428 PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
429 PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
430 PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
431 PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
432 PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
433 PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
434 PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
435 PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
437 PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
438 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
439 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
440 PMB_ADDR_NOT_USE_D: .long 0x00000000
442 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
443 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
444 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
446 /* ppn ub v s1 s0 c wt */
447 PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
448 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
449 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
451 PASCR_A: .long 0xff000070
452 DUMMY_ADDR: .long 0xa0000000
453 PASCR_29BIT_D: .long 0x00000000
454 PASCR_INIT: .long 0x80000080
455 MMUCR_A: .long 0xff000010
456 MMUCR_D: .long 0x00000004 /* clear ITLB */
457 #endif /* CONFIG_SH_32BIT */
460 CCR_D: .long CCR_CACHE_INIT