2 * Copyright (C) 2012 Renesas Solutions Corp.
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License. See the file "COPYING.LIB" in the main
6 * directory of this archive for more details.
11 #define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
12 #define CONFIG_SPI_ADDR 0x00000000
13 #define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
14 #define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
16 #define SPIWDMADR 0xFE001018
17 #define SPIWDMCNTR 0xFE001020
18 #define SPIDMCOR 0xFE001028
19 #define SPIDMINTSR 0xFE001188
20 #define SPIDMINTMR 0xFE001190
22 #define SPIDMINTSR_DMEND 0x00000004
24 #define TBR 0xFE002000
25 #define RBR 0xFE002000
27 #define CR1 0xFE002008
28 #define CR2 0xFE002010
29 #define CR3 0xFE002018
30 #define CR4 0xFE002020
37 #define SPI_PFONRD 0x08
44 #define SPI_LOOPBK 0x40
54 #define SPI_SpiS0 0x02
57 #define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
58 #define spi_read(addr) (*(volatile unsigned long *)(addr))
63 #define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
64 static void __uses_spiboot2 spi_reset(void)
66 int timeout = 0x00100000;
68 /* Make sure the last transaction is finalized */
71 while (!(spi_read(CR4) & SPI_SpiS0)) {
77 spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
78 spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
80 spi_write(0, SPIDMCOR);
83 static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
86 spi_write(M25_READ, TBR);
87 spi_write((addr >> 16) & 0xFF, TBR);
88 spi_write((addr >> 8) & 0xFF, TBR);
89 spi_write(addr & 0xFF, TBR);
91 spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
92 spi_write((unsigned long)buf, SPIWDMADR);
93 spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
94 spi_write(1, SPIDMCOR);
97 spi_write(spi_read(CR1) | SPI_SSDB, CR1);
98 spi_write(spi_read(CR1) | SPI_SSA, CR1);
100 while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
107 void __uses_spiboot2 spiboot_main(void)
109 void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
112 spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,