2 * Copyright (C) 2011 Renesas Solutions Corp.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
10 #include <asm/macro.h>
12 .macro or32, addr, data
26 .section .spiboot1.text
31 /*------- GPIO -------*/
32 write8 PGDR_A, PGDR_D /* eMMC power off */
34 write16 PACR_A, PACR_D
35 write16 PBCR_A, PBCR_D
36 write16 PCCR_A, PCCR_D
37 write16 PDCR_A, PDCR_D
38 write16 PECR_A, PECR_D
39 write16 PFCR_A, PFCR_D
40 write16 PGCR_A, PGCR_D
41 write16 PHCR_A, PHCR_D
42 write16 PICR_A, PICR_D
43 write16 PJCR_A, PJCR_D
44 write16 PKCR_A, PKCR_D
45 write16 PLCR_A, PLCR_D
46 write16 PMCR_A, PMCR_D
47 write16 PNCR_A, PNCR_D
48 write16 POCR_A, POCR_D
49 write16 PQCR_A, PQCR_D
50 write16 PRCR_A, PRCR_D
51 write16 PSCR_A, PSCR_D
52 write16 PTCR_A, PTCR_D
53 write16 PUCR_A, PUCR_D
54 write16 PVCR_A, PVCR_D
55 write16 PWCR_A, PWCR_D
56 write16 PXCR_A, PXCR_D
57 write16 PYCR_A, PYCR_D
58 write16 PZCR_A, PZCR_D
59 write16 PSEL0_A, PSEL0_D
60 write16 PSEL1_A, PSEL1_D
61 write16 PSEL2_A, PSEL2_D
62 write16 PSEL3_A, PSEL3_D
63 write16 PSEL4_A, PSEL4_D
64 write16 PSEL5_A, PSEL5_D
65 write16 PSEL6_A, PSEL6_D
66 write16 PSEL7_A, PSEL7_D
67 write16 PSEL8_A, PSEL8_D
74 /*------- GPIO -------*/
75 PGDR_A: .long 0xffec0040
76 PACR_A: .long 0xffec0000
77 PBCR_A: .long 0xffec0002
78 PCCR_A: .long 0xffec0004
79 PDCR_A: .long 0xffec0006
80 PECR_A: .long 0xffec0008
81 PFCR_A: .long 0xffec000a
82 PGCR_A: .long 0xffec000c
83 PHCR_A: .long 0xffec000e
84 PICR_A: .long 0xffec0010
85 PJCR_A: .long 0xffec0012
86 PKCR_A: .long 0xffec0014
87 PLCR_A: .long 0xffec0016
88 PMCR_A: .long 0xffec0018
89 PNCR_A: .long 0xffec001a
90 POCR_A: .long 0xffec001c
91 PQCR_A: .long 0xffec0020
92 PRCR_A: .long 0xffec0022
93 PSCR_A: .long 0xffec0024
94 PTCR_A: .long 0xffec0026
95 PUCR_A: .long 0xffec0028
96 PVCR_A: .long 0xffec002a
97 PWCR_A: .long 0xffec002c
98 PXCR_A: .long 0xffec002e
99 PYCR_A: .long 0xffec0030
100 PZCR_A: .long 0xffec0032
101 PSEL0_A: .long 0xffec0070
102 PSEL1_A: .long 0xffec0072
103 PSEL2_A: .long 0xffec0074
104 PSEL3_A: .long 0xffec0076
105 PSEL4_A: .long 0xffec0078
106 PSEL5_A: .long 0xffec007a
107 PSEL6_A: .long 0xffec007c
108 PSEL7_A: .long 0xffec0082
109 PSEL8_A: .long 0xffec0084
131 #if defined(CONFIG_SH7757_OFFSET_SPI)
141 PSEL0_D: .long 0xfe00
142 PSEL1_D: .long 0x0000
143 PSEL2_D: .long 0x3000
144 PSEL3_D: .long 0xff00
145 PSEL4_D: .long 0x771f
146 PSEL5_D: .long 0x0ffc
147 PSEL6_D: .long 0x00ff
148 PSEL7_D: .long 0xfc00
149 PSEL8_D: .long 0x0000
165 /* If CPU runs on SDRAM, PC is 0x8???????. */
166 PC_MASK: .long 0x20000000
173 mov.l EXPEVT_POWER_ON_RESET, r1
178 * If EXPEVT value is manual reset or tlb multipul-hit,
179 * initialization of DDR3IF is not necessary.
192 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
193 * initialization of DDR3-SDRAM.
199 /*------- DDR3IF -------*/
200 /* oscillation stabilization time */
201 wait_timer WAIT_OSC_TIME
204 write32 DBCMD_A, DBCMD_RSTL_VAL
208 write32 DBCMD_A, DBCMD_PDEN_VAL
211 write32 DBKIND_A, DBKIND_D
214 write32 DBCONF_A, DBCONF_D
215 write32 DBTR0_A, DBTR0_D
216 write32 DBTR1_A, DBTR1_D
217 write32 DBTR2_A, DBTR2_D
218 write32 DBTR3_A, DBTR3_D
219 write32 DBTR4_A, DBTR4_D
220 write32 DBTR5_A, DBTR5_D
221 write32 DBTR6_A, DBTR6_D
222 write32 DBTR7_A, DBTR7_D
223 write32 DBTR8_A, DBTR8_D
224 write32 DBTR9_A, DBTR9_D
225 write32 DBTR10_A, DBTR10_D
226 write32 DBTR11_A, DBTR11_D
227 write32 DBTR12_A, DBTR12_D
228 write32 DBTR13_A, DBTR13_D
229 write32 DBTR14_A, DBTR14_D
230 write32 DBTR15_A, DBTR15_D
231 write32 DBTR16_A, DBTR16_D
232 write32 DBTR17_A, DBTR17_D
233 write32 DBTR18_A, DBTR18_D
234 write32 DBTR19_A, DBTR19_D
235 write32 DBRNK0_A, DBRNK0_D
238 write32 DBPDCNT3_A, DBPDCNT3_D
241 write32 DBPDCNT1_A, DBPDCNT1_D
242 write32 DBPDCNT2_A, DBPDCNT2_D
243 write32 DBPDLCK_A, DBPDLCK_D
244 write32 DBPDRGA_A, DBPDRGA_D
245 write32 DBPDRGD_A, DBPDRGD_D
251 write32 DBPDCNT0_A, DBPDCNT0_D
258 write32 DBCMD_A, DBCMD_WAIT_VAL
262 write32 DBCMD_A, DBCMD_RSTH_VAL
266 write32 DBCMD_A, DBCMD_WAIT_VAL
267 write32 DBCMD_A, DBCMD_WAIT_VAL
268 write32 DBCMD_A, DBCMD_WAIT_VAL
269 write32 DBCMD_A, DBCMD_WAIT_VAL
272 write32 DBCMD_A, DBCMD_PDXT_VAL
275 write32 DBCMD_A, DBCMD_MRS2_VAL
278 write32 DBCMD_A, DBCMD_MRS3_VAL
281 write32 DBCMD_A, DBCMD_MRS1_VAL
284 write32 DBCMD_A, DBCMD_MRS0_VAL
287 write32 DBCMD_A, DBCMD_ZQCL_VAL
289 write32 DBCMD_A, DBCMD_REF_VAL
290 write32 DBCMD_A, DBCMD_REF_VAL
294 write32 DBADJ0_A, DBADJ0_D
295 write32 DBADJ1_A, DBADJ1_D
296 write32 DBADJ2_A, DBADJ2_D
299 write32 DBRFCNF0_A, DBRFCNF0_D
300 write32 DBRFCNF1_A, DBRFCNF1_D
301 write32 DBRFCNF2_A, DBRFCNF2_D
304 write32 DBCALCNF_A, DBCALCNF_D
307 write32 DBRFEN_A, DBRFEN_D
308 write32 DBCMD_A, DBCMD_SRXT_VAL
311 write32 DBACEN_A, DBACEN_D
316 #if defined(CONFIG_SH7757LCR_DDR_ECC)
318 write32 ECD_ECDEN_A, ECD_ECDEN_D
319 write32 ECD_INTSR_A, ECD_INTSR_D
320 write32 ECD_SPACER_A, ECD_SPACER_D
321 write32 ECD_MCR_A, ECD_MCR_D
328 EXPEVT_A: .long 0xff000024
329 EXPEVT_POWER_ON_RESET: .long 0x00000000
331 /*------- DDR3IF -------*/
332 DBCMD_A: .long 0xfe800018
333 DBKIND_A: .long 0xfe800020
334 DBCONF_A: .long 0xfe800024
335 DBTR0_A: .long 0xfe800040
336 DBTR1_A: .long 0xfe800044
337 DBTR2_A: .long 0xfe800048
338 DBTR3_A: .long 0xfe800050
339 DBTR4_A: .long 0xfe800054
340 DBTR5_A: .long 0xfe800058
341 DBTR6_A: .long 0xfe80005c
342 DBTR7_A: .long 0xfe800060
343 DBTR8_A: .long 0xfe800064
344 DBTR9_A: .long 0xfe800068
345 DBTR10_A: .long 0xfe80006c
346 DBTR11_A: .long 0xfe800070
347 DBTR12_A: .long 0xfe800074
348 DBTR13_A: .long 0xfe800078
349 DBTR14_A: .long 0xfe80007c
350 DBTR15_A: .long 0xfe800080
351 DBTR16_A: .long 0xfe800084
352 DBTR17_A: .long 0xfe800088
353 DBTR18_A: .long 0xfe80008c
354 DBTR19_A: .long 0xfe800090
355 DBRNK0_A: .long 0xfe800100
356 DBPDCNT0_A: .long 0xfe800200
357 DBPDCNT1_A: .long 0xfe800204
358 DBPDCNT2_A: .long 0xfe800208
359 DBPDCNT3_A: .long 0xfe80020c
360 DBPDLCK_A: .long 0xfe800280
361 DBPDRGA_A: .long 0xfe800290
362 DBPDRGD_A: .long 0xfe8002a0
363 DBADJ0_A: .long 0xfe8000c0
364 DBADJ1_A: .long 0xfe8000c4
365 DBADJ2_A: .long 0xfe8000c8
366 DBRFCNF0_A: .long 0xfe8000e0
367 DBRFCNF1_A: .long 0xfe8000e4
368 DBRFCNF2_A: .long 0xfe8000e8
369 DBCALCNF_A: .long 0xfe8000f4
370 DBRFEN_A: .long 0xfe800014
371 DBACEN_A: .long 0xfe800010
372 DBWAIT_A: .long 0xfe80001c
374 WAIT_OSC_TIME: .long 6000
375 WAIT_30US: .long 13333
377 DBCMD_RSTL_VAL: .long 0x20000000
378 DBCMD_PDEN_VAL: .long 0x1000d73c
379 DBCMD_WAIT_VAL: .long 0x0000d73c
380 DBCMD_RSTH_VAL: .long 0x2100d73c
381 DBCMD_PDXT_VAL: .long 0x110000c8
382 DBCMD_MRS0_VAL: .long 0x28000930
383 DBCMD_MRS1_VAL: .long 0x29000004
384 DBCMD_MRS2_VAL: .long 0x2a000008
385 DBCMD_MRS3_VAL: .long 0x2b000000
386 DBCMD_ZQCL_VAL: .long 0x03000200
387 DBCMD_REF_VAL: .long 0x0c000000
388 DBCMD_SRXT_VAL: .long 0x19000000
389 DBKIND_D: .long 0x00000007
390 DBCONF_D: .long 0x0f030a01
391 DBTR0_D: .long 0x00000007
392 DBTR1_D: .long 0x00000006
393 DBTR2_D: .long 0x00000000
394 DBTR3_D: .long 0x00000007
395 DBTR4_D: .long 0x00070007
396 DBTR5_D: .long 0x0000001b
397 DBTR6_D: .long 0x00000014
398 DBTR7_D: .long 0x00000005
399 DBTR8_D: .long 0x00000015
400 DBTR9_D: .long 0x00000006
401 DBTR10_D: .long 0x00000008
402 DBTR11_D: .long 0x00000007
403 DBTR12_D: .long 0x0000000e
404 DBTR13_D: .long 0x00000056
405 DBTR14_D: .long 0x00000006
406 DBTR15_D: .long 0x00000004
407 DBTR16_D: .long 0x00150002
408 DBTR17_D: .long 0x000c0017
409 DBTR18_D: .long 0x00000200
410 DBTR19_D: .long 0x00000040
411 DBRNK0_D: .long 0x00000001
412 DBPDCNT0_D: .long 0x00000001
413 DBPDCNT1_D: .long 0x00000001
414 DBPDCNT2_D: .long 0x00000000
415 DBPDCNT3_D: .long 0x00004010
416 DBPDLCK_D: .long 0x0000a55a
417 DBPDRGA_D: .long 0x00000028
418 DBPDRGD_D: .long 0x00017100
420 DBADJ0_D: .long 0x00000000
421 DBADJ1_D: .long 0x00000000
422 DBADJ2_D: .long 0x18061806
423 DBRFCNF0_D: .long 0x000001ff
424 DBRFCNF1_D: .long 0x08001000
425 DBRFCNF2_D: .long 0x00000000
426 DBCALCNF_D: .long 0x0000ffff
427 DBRFEN_D: .long 0x00000001
428 DBACEN_D: .long 0x00000001
430 /*------- DDR-ECC -------*/
431 ECD_ECDEN_A: .long 0xffc1012c
432 ECD_ECDEN_D: .long 0x00000001
433 ECD_INTSR_A: .long 0xfe900024
434 ECD_INTSR_D: .long 0xffffffff
435 ECD_SPACER_A: .long 0xfe900018
436 ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
437 ECD_MCR_A: .long 0xfe900010
438 ECD_MCR_D: .long 0x00000001
443 #if defined(CONFIG_SH_32BIT)
444 /*------- set PMB -------*/
445 write32 PASCR_A, PASCR_29BIT_D
446 write32 MMUCR_A, MMUCR_D
448 /*****************************************************************
449 * ent virt phys v sz c wt
450 * 0 0xa0000000 0x00000000 1 128M 0 1
451 * 1 0xa8000000 0x48000000 1 128M 0 1
452 * 5 0x88000000 0x48000000 1 128M 1 1
454 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
455 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
456 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
457 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
458 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
459 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
461 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
462 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
463 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
464 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
465 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
466 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
467 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
468 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
469 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
470 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
471 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
472 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
473 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
475 write32 PASCR_A, PASCR_INIT
478 #endif /* if defined(CONFIG_SH_32BIT) */
481 /* CPU is running on ILRAM? */
486 mov.l _bss_start, r15
487 mov.l _spiboot_main, r0
492 _spiboot_main: .long (spiboot_main - (100b + 4))
493 _bss_start: .long bss_start
504 #if defined(CONFIG_SH_32BIT)
505 /*------- set PMB -------*/
506 PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
507 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
508 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
509 PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
510 PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
511 PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
512 PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
513 PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
514 PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
515 PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
516 PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
517 PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
518 PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
519 PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
520 PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
521 PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
523 PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
524 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
525 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
526 PMB_ADDR_NOT_USE_D: .long 0x00000000
528 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
529 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
530 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
532 /* ppn ub v s1 s0 c wt */
533 PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
534 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
535 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
537 PASCR_A: .long 0xff000070
538 DUMMY_ADDR: .long 0xa0000000
539 PASCR_29BIT_D: .long 0x00000000
540 PASCR_INIT: .long 0x80000080
541 MMUCR_A: .long 0xff000010
542 MMUCR_D: .long 0x00000004 /* clear ITLB */
543 #endif /* CONFIG_SH_32BIT */
546 CCR_D: .long CCR_CACHE_INIT