2 * Copyright (C) 2011 Renesas Solutions Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/processor.h>
23 #include <asm/macro.h>
25 .macro or32, addr, data
39 .section .spiboot1.text
44 /*------- GPIO -------*/
45 write8 PGDR_A, PGDR_D /* eMMC power off */
47 write16 PACR_A, PACR_D
48 write16 PBCR_A, PBCR_D
49 write16 PCCR_A, PCCR_D
50 write16 PDCR_A, PDCR_D
51 write16 PECR_A, PECR_D
52 write16 PFCR_A, PFCR_D
53 write16 PGCR_A, PGCR_D
54 write16 PHCR_A, PHCR_D
55 write16 PICR_A, PICR_D
56 write16 PJCR_A, PJCR_D
57 write16 PKCR_A, PKCR_D
58 write16 PLCR_A, PLCR_D
59 write16 PMCR_A, PMCR_D
60 write16 PNCR_A, PNCR_D
61 write16 POCR_A, POCR_D
62 write16 PQCR_A, PQCR_D
63 write16 PRCR_A, PRCR_D
64 write16 PSCR_A, PSCR_D
65 write16 PTCR_A, PTCR_D
66 write16 PUCR_A, PUCR_D
67 write16 PVCR_A, PVCR_D
68 write16 PWCR_A, PWCR_D
69 write16 PXCR_A, PXCR_D
70 write16 PYCR_A, PYCR_D
71 write16 PZCR_A, PZCR_D
72 write16 PSEL0_A, PSEL0_D
73 write16 PSEL1_A, PSEL1_D
74 write16 PSEL2_A, PSEL2_D
75 write16 PSEL3_A, PSEL3_D
76 write16 PSEL4_A, PSEL4_D
77 write16 PSEL5_A, PSEL5_D
78 write16 PSEL6_A, PSEL6_D
79 write16 PSEL7_A, PSEL7_D
80 write16 PSEL8_A, PSEL8_D
87 /*------- GPIO -------*/
88 PGDR_A: .long 0xffec0040
89 PACR_A: .long 0xffec0000
90 PBCR_A: .long 0xffec0002
91 PCCR_A: .long 0xffec0004
92 PDCR_A: .long 0xffec0006
93 PECR_A: .long 0xffec0008
94 PFCR_A: .long 0xffec000a
95 PGCR_A: .long 0xffec000c
96 PHCR_A: .long 0xffec000e
97 PICR_A: .long 0xffec0010
98 PJCR_A: .long 0xffec0012
99 PKCR_A: .long 0xffec0014
100 PLCR_A: .long 0xffec0016
101 PMCR_A: .long 0xffec0018
102 PNCR_A: .long 0xffec001a
103 POCR_A: .long 0xffec001c
104 PQCR_A: .long 0xffec0020
105 PRCR_A: .long 0xffec0022
106 PSCR_A: .long 0xffec0024
107 PTCR_A: .long 0xffec0026
108 PUCR_A: .long 0xffec0028
109 PVCR_A: .long 0xffec002a
110 PWCR_A: .long 0xffec002c
111 PXCR_A: .long 0xffec002e
112 PYCR_A: .long 0xffec0030
113 PZCR_A: .long 0xffec0032
114 PSEL0_A: .long 0xffec0070
115 PSEL1_A: .long 0xffec0072
116 PSEL2_A: .long 0xffec0074
117 PSEL3_A: .long 0xffec0076
118 PSEL4_A: .long 0xffec0078
119 PSEL5_A: .long 0xffec007a
120 PSEL6_A: .long 0xffec007c
121 PSEL7_A: .long 0xffec0082
122 PSEL8_A: .long 0xffec0084
144 #if defined(CONFIG_SH7757_OFFSET_SPI)
154 PSEL0_D: .long 0xfe00
155 PSEL1_D: .long 0x0000
156 PSEL2_D: .long 0x3000
157 PSEL3_D: .long 0xff00
158 PSEL4_D: .long 0x771f
159 PSEL5_D: .long 0x0ffc
160 PSEL6_D: .long 0x00ff
161 PSEL7_D: .long 0xfc00
162 PSEL8_D: .long 0x0000
178 /* If CPU runs on SDRAM, PC is 0x8???????. */
179 PC_MASK: .long 0x20000000
186 mov.l EXPEVT_POWER_ON_RESET, r1
191 * If EXPEVT value is manual reset or tlb multipul-hit,
192 * initialization of DDR3IF is not necessary.
205 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
206 * initialization of DDR3-SDRAM.
212 /*------- DDR3IF -------*/
213 /* oscillation stabilization time */
214 wait_timer WAIT_OSC_TIME
217 write32 DBCMD_A, DBCMD_RSTL_VAL
221 write32 DBCMD_A, DBCMD_PDEN_VAL
224 write32 DBKIND_A, DBKIND_D
227 write32 DBCONF_A, DBCONF_D
228 write32 DBTR0_A, DBTR0_D
229 write32 DBTR1_A, DBTR1_D
230 write32 DBTR2_A, DBTR2_D
231 write32 DBTR3_A, DBTR3_D
232 write32 DBTR4_A, DBTR4_D
233 write32 DBTR5_A, DBTR5_D
234 write32 DBTR6_A, DBTR6_D
235 write32 DBTR7_A, DBTR7_D
236 write32 DBTR8_A, DBTR8_D
237 write32 DBTR9_A, DBTR9_D
238 write32 DBTR10_A, DBTR10_D
239 write32 DBTR11_A, DBTR11_D
240 write32 DBTR12_A, DBTR12_D
241 write32 DBTR13_A, DBTR13_D
242 write32 DBTR14_A, DBTR14_D
243 write32 DBTR15_A, DBTR15_D
244 write32 DBTR16_A, DBTR16_D
245 write32 DBTR17_A, DBTR17_D
246 write32 DBTR18_A, DBTR18_D
247 write32 DBTR19_A, DBTR19_D
248 write32 DBRNK0_A, DBRNK0_D
251 write32 DBPDCNT3_A, DBPDCNT3_D
254 write32 DBPDCNT1_A, DBPDCNT1_D
255 write32 DBPDCNT2_A, DBPDCNT2_D
256 write32 DBPDLCK_A, DBPDLCK_D
257 write32 DBPDRGA_A, DBPDRGA_D
258 write32 DBPDRGD_A, DBPDRGD_D
264 write32 DBPDCNT0_A, DBPDCNT0_D
271 write32 DBCMD_A, DBCMD_WAIT_VAL
275 write32 DBCMD_A, DBCMD_RSTH_VAL
279 write32 DBCMD_A, DBCMD_WAIT_VAL
280 write32 DBCMD_A, DBCMD_WAIT_VAL
281 write32 DBCMD_A, DBCMD_WAIT_VAL
282 write32 DBCMD_A, DBCMD_WAIT_VAL
285 write32 DBCMD_A, DBCMD_PDXT_VAL
288 write32 DBCMD_A, DBCMD_MRS2_VAL
291 write32 DBCMD_A, DBCMD_MRS3_VAL
294 write32 DBCMD_A, DBCMD_MRS1_VAL
297 write32 DBCMD_A, DBCMD_MRS0_VAL
300 write32 DBCMD_A, DBCMD_ZQCL_VAL
302 write32 DBCMD_A, DBCMD_REF_VAL
303 write32 DBCMD_A, DBCMD_REF_VAL
307 write32 DBADJ0_A, DBADJ0_D
308 write32 DBADJ1_A, DBADJ1_D
309 write32 DBADJ2_A, DBADJ2_D
312 write32 DBRFCNF0_A, DBRFCNF0_D
313 write32 DBRFCNF1_A, DBRFCNF1_D
314 write32 DBRFCNF2_A, DBRFCNF2_D
317 write32 DBCALCNF_A, DBCALCNF_D
320 write32 DBRFEN_A, DBRFEN_D
321 write32 DBCMD_A, DBCMD_SRXT_VAL
324 write32 DBACEN_A, DBACEN_D
330 write32 ECD_ECDEN_A, ECD_ECDEN_D
331 write32 ECD_INTSR_A, ECD_INTSR_D
332 write32 ECD_SPACER_A, ECD_SPACER_D
333 write32 ECD_MCR_A, ECD_MCR_D
340 EXPEVT_A: .long 0xff000024
341 EXPEVT_POWER_ON_RESET: .long 0x00000000
343 /*------- DDR3IF -------*/
344 DBCMD_A: .long 0xfe800018
345 DBKIND_A: .long 0xfe800020
346 DBCONF_A: .long 0xfe800024
347 DBTR0_A: .long 0xfe800040
348 DBTR1_A: .long 0xfe800044
349 DBTR2_A: .long 0xfe800048
350 DBTR3_A: .long 0xfe800050
351 DBTR4_A: .long 0xfe800054
352 DBTR5_A: .long 0xfe800058
353 DBTR6_A: .long 0xfe80005c
354 DBTR7_A: .long 0xfe800060
355 DBTR8_A: .long 0xfe800064
356 DBTR9_A: .long 0xfe800068
357 DBTR10_A: .long 0xfe80006c
358 DBTR11_A: .long 0xfe800070
359 DBTR12_A: .long 0xfe800074
360 DBTR13_A: .long 0xfe800078
361 DBTR14_A: .long 0xfe80007c
362 DBTR15_A: .long 0xfe800080
363 DBTR16_A: .long 0xfe800084
364 DBTR17_A: .long 0xfe800088
365 DBTR18_A: .long 0xfe80008c
366 DBTR19_A: .long 0xfe800090
367 DBRNK0_A: .long 0xfe800100
368 DBPDCNT0_A: .long 0xfe800200
369 DBPDCNT1_A: .long 0xfe800204
370 DBPDCNT2_A: .long 0xfe800208
371 DBPDCNT3_A: .long 0xfe80020c
372 DBPDLCK_A: .long 0xfe800280
373 DBPDRGA_A: .long 0xfe800290
374 DBPDRGD_A: .long 0xfe8002a0
375 DBADJ0_A: .long 0xfe8000c0
376 DBADJ1_A: .long 0xfe8000c4
377 DBADJ2_A: .long 0xfe8000c8
378 DBRFCNF0_A: .long 0xfe8000e0
379 DBRFCNF1_A: .long 0xfe8000e4
380 DBRFCNF2_A: .long 0xfe8000e8
381 DBCALCNF_A: .long 0xfe8000f4
382 DBRFEN_A: .long 0xfe800014
383 DBACEN_A: .long 0xfe800010
384 DBWAIT_A: .long 0xfe80001c
386 WAIT_OSC_TIME: .long 6000
387 WAIT_30US: .long 13333
389 DBCMD_RSTL_VAL: .long 0x20000000
390 DBCMD_PDEN_VAL: .long 0x1000d73c
391 DBCMD_WAIT_VAL: .long 0x0000d73c
392 DBCMD_RSTH_VAL: .long 0x2100d73c
393 DBCMD_PDXT_VAL: .long 0x110000c8
394 DBCMD_MRS0_VAL: .long 0x28000930
395 DBCMD_MRS1_VAL: .long 0x29000004
396 DBCMD_MRS2_VAL: .long 0x2a000008
397 DBCMD_MRS3_VAL: .long 0x2b000000
398 DBCMD_ZQCL_VAL: .long 0x03000200
399 DBCMD_REF_VAL: .long 0x0c000000
400 DBCMD_SRXT_VAL: .long 0x19000000
401 DBKIND_D: .long 0x00000007
402 DBCONF_D: .long 0x0f030a01
403 DBTR0_D: .long 0x00000007
404 DBTR1_D: .long 0x00000006
405 DBTR2_D: .long 0x00000000
406 DBTR3_D: .long 0x00000007
407 DBTR4_D: .long 0x00070007
408 DBTR5_D: .long 0x0000001b
409 DBTR6_D: .long 0x00000014
410 DBTR7_D: .long 0x00000005
411 DBTR8_D: .long 0x00000015
412 DBTR9_D: .long 0x00000006
413 DBTR10_D: .long 0x00000008
414 DBTR11_D: .long 0x00000007
415 DBTR12_D: .long 0x0000000e
416 DBTR13_D: .long 0x00000056
417 DBTR14_D: .long 0x00000006
418 DBTR15_D: .long 0x00000004
419 DBTR16_D: .long 0x00150002
420 DBTR17_D: .long 0x000c0017
421 DBTR18_D: .long 0x00000200
422 DBTR19_D: .long 0x00000040
423 DBRNK0_D: .long 0x00000001
424 DBPDCNT0_D: .long 0x00000001
425 DBPDCNT1_D: .long 0x00000001
426 DBPDCNT2_D: .long 0x00000000
427 DBPDCNT3_D: .long 0x00004010
428 DBPDLCK_D: .long 0x0000a55a
429 DBPDRGA_D: .long 0x00000028
430 DBPDRGD_D: .long 0x00017100
432 DBADJ0_D: .long 0x00000000
433 DBADJ1_D: .long 0x00000000
434 DBADJ2_D: .long 0x18061806
435 DBRFCNF0_D: .long 0x000001ff
436 DBRFCNF1_D: .long 0x08001000
437 DBRFCNF2_D: .long 0x00000000
438 DBCALCNF_D: .long 0x0000ffff
439 DBRFEN_D: .long 0x00000001
440 DBACEN_D: .long 0x00000001
442 /*------- DDR-ECC -------*/
443 ECD_ECDEN_A: .long 0xffc1012c
444 ECD_ECDEN_D: .long 0x00000001
445 ECD_INTSR_A: .long 0xfe900024
446 ECD_INTSR_D: .long 0xffffffff
447 ECD_SPACER_A: .long 0xfe900018
448 ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
449 ECD_MCR_A: .long 0xfe900010
450 ECD_MCR_D: .long 0x00000001
455 #if defined(CONFIG_SH_32BIT)
456 /*------- set PMB -------*/
457 write32 PASCR_A, PASCR_29BIT_D
458 write32 MMUCR_A, MMUCR_D
460 /*****************************************************************
461 * ent virt phys v sz c wt
462 * 0 0xa0000000 0x00000000 1 128M 0 1
463 * 1 0xa8000000 0x48000000 1 128M 0 1
464 * 5 0x88000000 0x48000000 1 128M 1 1
466 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
467 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
468 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
469 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
470 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
471 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
473 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
474 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
475 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
476 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
477 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
478 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
479 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
480 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
481 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
482 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
483 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
484 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
485 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
487 write32 PASCR_A, PASCR_INIT
490 #endif /* if defined(CONFIG_SH_32BIT) */
493 /* CPU is running on ILRAM? */
498 mov.l _bss_start, r15
499 mov.l _spiboot_main, r0
504 _spiboot_main: .long (spiboot_main - (100b + 4))
505 _bss_start: .long bss_start
516 #if defined(CONFIG_SH_32BIT)
517 /*------- set PMB -------*/
518 PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
519 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
520 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
521 PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
522 PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
523 PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
524 PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
525 PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
526 PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
527 PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
528 PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
529 PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
530 PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
531 PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
532 PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
533 PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
535 PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
536 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
537 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
538 PMB_ADDR_NOT_USE_D: .long 0x00000000
540 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
541 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
542 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
544 /* ppn ub v s1 s0 c wt */
545 PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
546 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
547 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
549 PASCR_A: .long 0xff000070
550 DUMMY_ADDR: .long 0xa0000000
551 PASCR_29BIT_D: .long 0x00000000
552 PASCR_INIT: .long 0x80000080
553 MMUCR_A: .long 0xff000010
554 MMUCR_D: .long 0x00000004 /* clear ITLB */
555 #endif /* CONFIG_SH_32BIT */
558 CCR_D: .long CCR_CACHE_INIT