2 * Copyright (C) 2011 Renesas Solutions Corp.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
12 #include <spi_flash.h>
16 puts("BOARD: R0P7757LC0030RL board\n");
21 static void init_gctrl(void)
23 struct gctrl_regs *gctrl = GCTRL_BASE;
24 unsigned long graofst;
26 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
27 writel(graofst | 0x20000f00, &gctrl->gracr3);
30 static int init_pcie_bridge_from_spi(void *buf, size_t size)
32 struct spi_flash *spi;
34 unsigned long pcie_addr;
36 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
38 printf("%s: spi_flash probe error.\n", __func__);
43 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
45 pcie_addr = SH7757LCR_PCIEBRG_ADDR;
47 ret = spi_flash_read(spi, pcie_addr, size, buf);
49 printf("%s: spi_flash read error.\n", __func__);
58 static void init_pcie_bridge(void)
60 struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
61 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
65 unsigned long pcie_size;
67 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
71 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
73 pcie_size = SH7757LCR_PCIEBRG_SIZE;
75 data = malloc(pcie_size);
77 printf("%s: malloc error.\n", __func__);
80 if (init_pcie_bridge_from_spi(data, pcie_size)) {
85 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
88 printf("%s: skipped initialization\n", __func__);
92 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
93 writew(0x0000, &pciebrg->cp_ctrl);
94 writew(0x0000, &pciebrg->cp_addr);
96 for (i = 0; i < pcie_size; i += 2) {
97 tmp = (data[i] << 8) | data[i + 1];
98 writew(tmp, &pciebrg->cp_data);
101 writew(0xa500, &pciebrg->ctrl_h8s); /* start */
103 writel(0x00000001, &pcie_setup->pbictl3);
108 static void init_usb_phy(void)
110 struct usb_common_regs *common0 = USB0_COMMON_BASE;
111 struct usb_common_regs *common1 = USB1_COMMON_BASE;
112 struct usb0_phy_regs *phy = USB0_PHY_BASE;
113 struct usb1_port_regs *port = USB1_PORT_BASE;
114 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
116 writew(0x0100, &phy->reset); /* set reset */
117 /* port0 = USB0, port1 = USB1 */
118 writew(0x0002, &phy->portsel);
119 writel(0x0001, &port->port1sel); /* port1 = Host */
120 writew(0x0111, &phy->reset); /* clear reset */
122 writew(0x4000, &common0->suspmode);
123 writew(0x4000, &common1->suspmode);
125 #if defined(__LITTLE_ENDIAN)
126 writel(0x00000000, &align->ehcidatac);
127 writel(0x00000000, &align->ohcidatac);
131 static void set_mac_to_sh_eth_register(int channel, char *mac_string)
133 struct ether_mac_regs *ether;
134 unsigned char mac[6];
137 eth_parse_enetaddr(mac_string, mac);
140 ether = ETHER0_MAC_BASE;
142 ether = ETHER1_MAC_BASE;
144 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
145 writel(val, ðer->mahr);
146 val = (mac[4] << 8) | mac[5];
147 writel(val, ðer->malr);
150 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
152 struct ether_mac_regs *ether;
153 unsigned char mac[6];
156 eth_parse_enetaddr(mac_string, mac);
159 ether = GETHER0_MAC_BASE;
161 ether = GETHER1_MAC_BASE;
163 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
164 writel(val, ðer->mahr);
165 val = (mac[4] << 8) | mac[5];
166 writel(val, ðer->malr);
169 /*****************************************************************
170 * This PMB must be set on this timing. The lowlevel_init is run on
171 * Area 0(phys 0x00000000), so we have to map it.
173 * The new PMB table is following:
174 * ent virt phys v sz c wt
175 * 0 0xa0000000 0x40000000 1 128M 0 1
176 * 1 0xa8000000 0x48000000 1 128M 0 1
177 * 2 0xb0000000 0x50000000 1 128M 0 1
178 * 3 0xb8000000 0x58000000 1 128M 0 1
179 * 4 0x80000000 0x40000000 1 128M 1 1
180 * 5 0x88000000 0x48000000 1 128M 1 1
181 * 6 0x90000000 0x50000000 1 128M 1 1
182 * 7 0x98000000 0x58000000 1 128M 1 1
184 static void set_pmb_on_board_init(void)
186 struct mmu_regs *mmu = MMU_BASE;
189 writel(0x00000004, &mmu->mmucr);
191 /* delete PMB for SPIBOOT */
192 writel(0, PMB_ADDR_BASE(0));
193 writel(0, PMB_DATA_BASE(0));
195 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
196 /* ppn ub v s1 s0 c wt */
197 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
198 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
199 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
200 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
201 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
202 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
203 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
204 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
205 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
206 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
207 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
208 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
213 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
215 set_pmb_on_board_init();
217 /* enable RMII's MDIO (disable GRMII's MDIO) */
218 writel(0x00030000, &gether->gbecont);
228 DECLARE_GLOBAL_DATA_PTR;
230 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
231 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
232 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
233 printf(" Physical address\n");
234 printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",
235 SH7757LCR_SDRAM_PHYS_TOP,
236 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
237 printf(" 0x%08x - 0x%08x : No Access Area\n",
238 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
239 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
240 printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
241 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
242 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
243 SH7757LCR_SDRAM_DVC_SIZE - 1);
244 printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
245 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
246 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
251 int board_mmc_init(bd_t *bis)
253 return mmcif_mmc_init();
256 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
258 struct spi_flash *spi;
261 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
263 printf("%s: spi_flash probe error.\n", __func__);
267 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
269 printf("%s: spi_flash read error.\n", __func__);
278 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
280 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
281 SH7757LCR_ETHERNET_MAC_SIZE);
282 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
287 static void init_ethernet_mac(void)
296 printf("%s: malloc error.\n", __func__);
299 get_sh_eth_mac_raw(buf, 256);
302 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
303 get_sh_eth_mac(i, mac_string, buf);
305 setenv("ethaddr", mac_string);
307 sprintf(env_string, "eth%daddr", i);
308 setenv(env_string, mac_string);
311 set_mac_to_sh_eth_register(i, mac_string);
314 /* Gigabit Ethernet */
315 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
316 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
317 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
318 setenv(env_string, mac_string);
320 set_mac_to_sh_giga_eth_register(i, mac_string);
326 static void init_pcie(void)
328 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
329 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
331 writel(0x00000ff2, &pcie_setup->ladmsk0);
332 writel(0x00000001, &pcie_setup->barmap);
333 writel(0xffcaa000, &pcie_setup->lad0);
334 writel(0x00030000, &pcie_sysbus->endictl0);
335 writel(0x00000003, &pcie_sysbus->endictl1);
336 writel(0x00000004, &pcie_setup->pbictl2);
339 static void finish_spiboot(void)
341 struct gctrl_regs *gctrl = GCTRL_BASE;
343 * SH7757 B0 does not use LBSC.
344 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
345 * This setting is not cleared by manual reset, So we have to set it
348 writel(0x00000000, &gctrl->spibootcan);
351 int board_late_init(void)
361 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
363 struct gctrl_regs *gctrl = GCTRL_BASE;
364 unsigned long graofst;
366 writel(0xfedcba98, &gctrl->wprotect);
367 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
368 writel(graofst | 0xa0000f00, &gctrl->gracr3);
374 sh_g200, 1, 1, do_sh_g200,
376 "enable SH-G200 bus (disable PCIe-G200)"
379 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
382 char mac_string[256];
383 struct spi_flash *spi;
389 printf("%s: malloc error.\n", __func__);
393 get_sh_eth_mac_raw(buf, 256);
395 /* print current MAC address */
396 for (i = 0; i < 4; i++) {
397 get_sh_eth_mac(i, mac_string, buf);
399 printf(" ETHERC ch%d = %s\n", i, mac_string);
401 printf("GETHERC ch%d = %s\n", i-2, mac_string);
408 memset(mac_string, 0xff, sizeof(mac_string));
409 sprintf(mac_string, "%s\t%s\t%s\t%s",
410 argv[1], argv[2], argv[3], argv[4]);
412 /* write MAC data to SPI rom */
413 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
415 printf("%s: spi_flash probe error.\n", __func__);
419 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
420 SH7757LCR_SPI_SECTOR_SIZE);
422 printf("%s: spi_flash erase error.\n", __func__);
426 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
427 sizeof(mac_string), mac_string);
429 printf("%s: spi_flash write error.\n", __func__);
435 puts("The writing of the MAC address to SPI ROM was completed.\n");
441 write_mac, 5, 1, do_write_mac,
442 "write MAC address for ETHERC/GETHERC",
443 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"