2 * Copyright (C) 2011 Renesas Solutions Corp.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #include <spi_flash.h>
31 puts("BOARD: R0P7757LC0030RL board\n");
36 static void init_gctrl(void)
38 struct gctrl_regs *gctrl = GCTRL_BASE;
39 unsigned long graofst;
41 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
42 writel(graofst | 0x20000f00, &gctrl->gracr3);
45 static int init_pcie_bridge_from_spi(void *buf, size_t size)
47 struct spi_flash *spi;
49 unsigned long pcie_addr;
51 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
53 printf("%s: spi_flash probe error.\n", __func__);
58 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
60 pcie_addr = SH7757LCR_PCIEBRG_ADDR;
62 ret = spi_flash_read(spi, pcie_addr, size, buf);
64 printf("%s: spi_flash read error.\n", __func__);
73 static void init_pcie_bridge(void)
75 struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
76 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
80 unsigned long pcie_size;
82 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
86 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
88 pcie_size = SH7757LCR_PCIEBRG_SIZE;
90 data = malloc(pcie_size);
92 printf("%s: malloc error.\n", __func__);
95 if (init_pcie_bridge_from_spi(data, pcie_size)) {
100 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
103 printf("%s: skipped initialization\n", __func__);
107 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
108 writew(0x0000, &pciebrg->cp_ctrl);
109 writew(0x0000, &pciebrg->cp_addr);
111 for (i = 0; i < pcie_size; i += 2) {
112 tmp = (data[i] << 8) | data[i + 1];
113 writew(tmp, &pciebrg->cp_data);
116 writew(0xa500, &pciebrg->ctrl_h8s); /* start */
118 writel(0x00000001, &pcie_setup->pbictl3);
123 static void init_usb_phy(void)
125 struct usb_common_regs *common0 = USB0_COMMON_BASE;
126 struct usb_common_regs *common1 = USB1_COMMON_BASE;
127 struct usb0_phy_regs *phy = USB0_PHY_BASE;
128 struct usb1_port_regs *port = USB1_PORT_BASE;
129 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
131 writew(0x0100, &phy->reset); /* set reset */
132 /* port0 = USB0, port1 = USB1 */
133 writew(0x0002, &phy->portsel);
134 writel(0x0001, &port->port1sel); /* port1 = Host */
135 writew(0x0111, &phy->reset); /* clear reset */
137 writew(0x4000, &common0->suspmode);
138 writew(0x4000, &common1->suspmode);
140 #if defined(__LITTLE_ENDIAN)
141 writel(0x00000000, &align->ehcidatac);
142 writel(0x00000000, &align->ohcidatac);
146 static void set_mac_to_sh_eth_register(int channel, char *mac_string)
148 struct ether_mac_regs *ether;
149 unsigned char mac[6];
152 eth_parse_enetaddr(mac_string, mac);
155 ether = ETHER0_MAC_BASE;
157 ether = ETHER1_MAC_BASE;
159 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
160 writel(val, ðer->mahr);
161 val = (mac[4] << 8) | mac[5];
162 writel(val, ðer->malr);
165 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
167 struct ether_mac_regs *ether;
168 unsigned char mac[6];
171 eth_parse_enetaddr(mac_string, mac);
174 ether = GETHER0_MAC_BASE;
176 ether = GETHER1_MAC_BASE;
178 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
179 writel(val, ðer->mahr);
180 val = (mac[4] << 8) | mac[5];
181 writel(val, ðer->malr);
184 /*****************************************************************
185 * This PMB must be set on this timing. The lowlevel_init is run on
186 * Area 0(phys 0x00000000), so we have to map it.
188 * The new PMB table is following:
189 * ent virt phys v sz c wt
190 * 0 0xa0000000 0x40000000 1 128M 0 1
191 * 1 0xa8000000 0x48000000 1 128M 0 1
192 * 2 0xb0000000 0x50000000 1 128M 0 1
193 * 3 0xb8000000 0x58000000 1 128M 0 1
194 * 4 0x80000000 0x40000000 1 128M 1 1
195 * 5 0x88000000 0x48000000 1 128M 1 1
196 * 6 0x90000000 0x50000000 1 128M 1 1
197 * 7 0x98000000 0x58000000 1 128M 1 1
199 static void set_pmb_on_board_init(void)
201 struct mmu_regs *mmu = MMU_BASE;
204 writel(0x00000004, &mmu->mmucr);
206 /* delete PMB for SPIBOOT */
207 writel(0, PMB_ADDR_BASE(0));
208 writel(0, PMB_DATA_BASE(0));
210 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
211 /* ppn ub v s1 s0 c wt */
212 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
213 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
214 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
215 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
216 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
217 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
218 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
219 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
220 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
221 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
222 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
223 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
228 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
230 set_pmb_on_board_init();
232 /* enable RMII's MDIO (disable GRMII's MDIO) */
233 writel(0x00030000, &gether->gbecont);
243 DECLARE_GLOBAL_DATA_PTR;
245 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
246 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
247 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
248 printf(" Physical address\n");
249 printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",
250 SH7757LCR_SDRAM_PHYS_TOP,
251 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
252 printf(" 0x%08x - 0x%08x : No Access Area\n",
253 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
254 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
255 printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
256 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
257 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
258 SH7757LCR_SDRAM_DVC_SIZE - 1);
259 printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
260 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
261 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
266 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
268 struct spi_flash *spi;
271 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
273 printf("%s: spi_flash probe error.\n", __func__);
277 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
279 printf("%s: spi_flash read error.\n", __func__);
288 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
290 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
291 SH7757LCR_ETHERNET_MAC_SIZE);
292 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
297 static void init_ethernet_mac(void)
306 printf("%s: malloc error.\n", __func__);
309 get_sh_eth_mac_raw(buf, 256);
312 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
313 get_sh_eth_mac(i, mac_string, buf);
315 setenv("ethaddr", mac_string);
317 sprintf(env_string, "eth%daddr", i);
318 setenv(env_string, mac_string);
321 set_mac_to_sh_eth_register(i, mac_string);
324 /* Gigabit Ethernet */
325 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
326 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
327 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
328 setenv(env_string, mac_string);
330 set_mac_to_sh_giga_eth_register(i, mac_string);
336 static void init_pcie(void)
338 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
339 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
341 writel(0x00000ff2, &pcie_setup->ladmsk0);
342 writel(0x00000001, &pcie_setup->barmap);
343 writel(0xffcaa000, &pcie_setup->lad0);
344 writel(0x00030000, &pcie_sysbus->endictl0);
345 writel(0x00000003, &pcie_sysbus->endictl1);
346 writel(0x00000004, &pcie_setup->pbictl2);
349 static void finish_spiboot(void)
351 struct gctrl_regs *gctrl = GCTRL_BASE;
353 * SH7757 B0 does not use LBSC.
354 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
355 * This setting is not cleared by manual reset, So we have to set it
358 writel(0x00000000, &gctrl->spibootcan);
361 int board_late_init(void)
371 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
373 struct gctrl_regs *gctrl = GCTRL_BASE;
374 unsigned long graofst;
376 writel(0xfedcba98, &gctrl->wprotect);
377 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
378 writel(graofst | 0xa0000f00, &gctrl->gracr3);
384 sh_g200, 1, 1, do_sh_g200,
386 "enable SH-G200 bus (disable PCIe-G200)"
389 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
392 char mac_string[256];
393 struct spi_flash *spi;
399 printf("%s: malloc error.\n", __func__);
403 get_sh_eth_mac_raw(buf, 256);
405 /* print current MAC address */
406 for (i = 0; i < 4; i++) {
407 get_sh_eth_mac(i, mac_string, buf);
409 printf(" ETHERC ch%d = %s\n", i, mac_string);
411 printf("GETHERC ch%d = %s\n", i-2, mac_string);
418 memset(mac_string, 0xff, sizeof(mac_string));
419 sprintf(mac_string, "%s\t%s\t%s\t%s",
420 argv[1], argv[2], argv[3], argv[4]);
422 /* write MAC data to SPI rom */
423 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
425 printf("%s: spi_flash probe error.\n", __func__);
429 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
430 SH7757LCR_SPI_SECTOR_SIZE);
432 printf("%s: spi_flash erase error.\n", __func__);
436 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
437 sizeof(mac_string), mac_string);
439 printf("%s: spi_flash write error.\n", __func__);
445 puts("The writing of the MAC address to SPI ROM was completed.\n");
451 write_mac, 5, 1, do_write_mac,
452 "write MAC address for ETHERC/GETHERC",
453 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"