2 * Copyright (C) 2008 Renesas Solutions Corp.
3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
4 * Copyright (C) 2007 Kenati Technologies, Inc.
6 * board/sh7763rdp/lowlevel_init.S
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/macro.h>
37 write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
39 write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
41 write32 WDTBST_A, WDTBST_D /*
43 * Watchdog Base Stop Time Register
46 write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
47 /* Instruction Cache Invalidate */
49 write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
50 /* TI == TLB Invalidate bit */
52 write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
54 write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
56 write32 RAMCR_A, RAMCR_D
63 mov.l @r1, r2 /* execute two reads after setting MMSELR */
67 /* issue memory read */
68 mov.l DDRSD_START_A, r1 /* memory address to read*/
72 write32 MIM8_A, MIM8_D
74 write32 MIMC_A, MIMC_D1
76 write32 STRC_A, STRC_D
78 write32 SDR4_A, SDR4_D
80 write32 MIMC_A, MIMC_D2
86 write32 SCR4_A, SCR4_D3
88 write32 SCR4_A, SCR4_D2
90 write32 SDMR02000_A, SDMR02000_D
92 write32 SDMR00B08_A, SDMR00B08_D
94 write32 SCR4_A, SCR4_D2
96 write32 SCR4_A, SCR4_D4
103 write32 SCR4_A, SCR4_D4
110 write32 SDMR00308_A, SDMR00308_D
112 write32 MIMC_A, MIMC_D3
124 write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
129 write32 CS0BCR_A, CS0BCR_D
131 write32 CS1BCR_A, CS1BCR_D
133 write32 CS2BCR_A, CS2BCR_D
135 write32 CS4BCR_A, CS4BCR_D
137 write32 CS5BCR_A, CS5BCR_D
139 write32 CS6BCR_A, CS6BCR_D
141 write32 CS0WCR_A, CS0WCR_D
143 write32 CS1WCR_A, CS1WCR_D
145 write32 CS2WCR_A, CS2WCR_D
147 write32 CS4WCR_A, CS4WCR_D
149 write32 CS5WCR_A, CS5WCR_D
151 write32 CS6WCR_A, CS6WCR_D
153 write32 CS5PCR_A, CS5PCR_D
155 write32 CS6PCR_A, CS6PCR_D
164 write16 PSEL0_A, PSEL0_D
166 write16 PSEL1_A, PSEL1_D
168 write32 ICR0_A, ICR0_D
170 stc sr, r0 /* BL bit off(init=ON) */
181 DELAY200_D: .long 17800
183 CCR_A: .long 0xFF00001C
184 MMUCR_A: .long 0xFF000010
185 RAMCR_A: .long 0xFF000074
187 /* Low power mode control */
188 MSTPCR0_A: .long 0xFFC80030
189 MSTPCR1_A: .long 0xFFC80038
192 WDTST_A: .long 0xFFCC0000
193 WDTCSR_A: .long 0xFFCC0004
194 WDTBST_A: .long 0xFFCC0008
197 MMSELR_A: .long 0xFE600020
198 BCR_A: .long 0xFF801000
199 CS0BCR_A: .long 0xFF802000
200 CS1BCR_A: .long 0xFF802010
201 CS2BCR_A: .long 0xFF802020
202 CS4BCR_A: .long 0xFF802040
203 CS5BCR_A: .long 0xFF802050
204 CS6BCR_A: .long 0xFF802060
205 CS0WCR_A: .long 0xFF802008
206 CS1WCR_A: .long 0xFF802018
207 CS2WCR_A: .long 0xFF802028
208 CS4WCR_A: .long 0xFF802048
209 CS5WCR_A: .long 0xFF802058
210 CS6WCR_A: .long 0xFF802068
211 CS5PCR_A: .long 0xFF802070
212 CS6PCR_A: .long 0xFF802080
213 DDRSD_START_A: .long 0xAC000000
216 ICR0_A: .long 0xFFD00000
219 MIM8_A: .long 0xFE800008
220 MIMC_A: .long 0xFE80000C
221 SCR4_A: .long 0xFE800014
222 STRC_A: .long 0xFE80001C
223 SDR4_A: .long 0xFE800034
224 SDMR00308_A: .long 0xFE900308
225 SDMR00B08_A: .long 0xFE900B08
226 SDMR02000_A: .long 0xFE902000
229 PSEL0_A: .long 0xFFEF0070
230 PSEL1_A: .long 0xFFEF0072
232 CCR_CACHE_ICI_D:.long 0x00000800
233 CCR_CACHE_D_2: .long 0x00000103
234 MMU_CONTROL_TI_D:.long 0x00000004
235 RAMCR_D: .long 0x00000200
236 MSTPCR0_D: .long 0x00000000
237 MSTPCR1_D: .long 0x00000000
239 MMSELR_D: .long 0xa5a50000
240 BCR_D: .long 0x00000000
241 CS0BCR_D: .long 0x77777770
242 CS1BCR_D: .long 0x77777670
243 CS2BCR_D: .long 0x77777670
244 CS4BCR_D: .long 0x77777670
245 CS5BCR_D: .long 0x77777670
246 CS6BCR_D: .long 0x77777670
247 CS0WCR_D: .long 0x7777770F
248 CS1WCR_D: .long 0x22000002
249 CS2WCR_D: .long 0x7777770F
250 CS4WCR_D: .long 0x7777770F
251 CS5WCR_D: .long 0x7777770F
252 CS6WCR_D: .long 0x7777770F
253 CS5PCR_D: .long 0x77000000
254 CS6PCR_D: .long 0x77000000
255 ICR0_D: .long 0x00E00000
256 MIM8_D: .long 0x00000000
257 MIMC_D1: .long 0x01d10008
258 MIMC_D2: .long 0x01d10009
259 MIMC_D3: .long 0x01d10209
260 SCR4_D1: .long 0x00000001
261 SCR4_D2: .long 0x00000002
262 SCR4_D3: .long 0x00000003
263 SCR4_D4: .long 0x00000004
264 STRC_D: .long 0x000f3980
265 SDR4_D: .long 0x00000300
266 SDMR00308_D: .long 0x00000000
267 SDMR00B08_D: .long 0x00000000
268 SDMR02000_D: .long 0x00000000
269 PSEL0_D: .long 0x00000001
270 PSEL1_D: .long 0x00000244
271 SR_MASK_D: .long 0xEFFFFF0F
272 WDTST_D: .long 0x5A000FFF
273 WDTCSR_D: .long 0xA5000000
274 WDTBST_D: .long 0x55000000