2 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/processor.h>
10 #include <asm/processor.h>
21 /*------- LBSC -------*/
22 write32 MMSELR_A, MMSELR_D
24 /*------- DBSC2 -------*/
25 write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
26 write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
27 write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
28 write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
29 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
30 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
33 write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
34 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
36 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
37 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
38 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
39 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
40 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
41 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
42 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
43 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
44 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
47 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
48 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
50 write32 DBSC2_DBEN_A, DBSC2_DBEN_D
51 write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
52 write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
53 write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
56 /*------- GPIO -------*/
57 write16 PACR_A, PXCR_D
58 write16 PBCR_A, PXCR_D
59 write16 PCCR_A, PXCR_D
60 write16 PDCR_A, PXCR_D
61 write16 PECR_A, PXCR_D
62 write16 PFCR_A, PXCR_D
63 write16 PGCR_A, PXCR_D
64 write16 PHCR_A, PHCR_D
65 write16 PJCR_A, PJCR_D
66 write16 PKCR_A, PKCR_D
67 write16 PLCR_A, PXCR_D
68 write16 PMCR_A, PMCR_D
69 write16 PNCR_A, PNCR_D
70 write16 PPCR_A, PXCR_D
71 write16 PQCR_A, PXCR_D
72 write16 PRCR_A, PXCR_D
74 write8 PEPUPR_A, PEPUPR_D
75 write8 PHPUPR_A, PHPUPR_D
76 write8 PJPUPR_A, PJPUPR_D
77 write8 PKPUPR_A, PKPUPR_D
78 write8 PLPUPR_A, PLPUPR_D
79 write8 PMPUPR_A, PMPUPR_D
80 write8 PNPUPR_A, PNPUPR_D
81 write16 PPUPR1_A, PPUPR1_D
82 write16 PPUPR2_A, PPUPR2_D
83 write16 P1MSELR_A, P1MSELR_D
84 write16 P2MSELR_A, P2MSELR_D
86 /*------- LBSC -------*/
88 write32 CS0BCR_A, CS0BCR_D
89 write32 CS0WCR_A, CS0WCR_D
90 write32 CS1BCR_A, CS1BCR_D
91 write32 CS1WCR_A, CS1WCR_D
92 write32 CS4BCR_A, CS4BCR_D
93 write32 CS4WCR_A, CS4WCR_D
97 mov.l PASCR_32BIT_MODE, r1
101 write32 CS2BCR_A, CS_USB_BCR_D
102 write32 CS2WCR_A, CS_USB_WCR_D
103 write32 CS3BCR_A, CS_SD_BCR_D
104 write32 CS3WCR_A, CS_SD_WCR_D
105 write32 CS5BCR_A, CS_I2C_BCR_D
106 write32 CS5WCR_A, CS_I2C_WCR_D
107 write32 CS6BCR_A, CS0BCR_D
108 write32 CS6WCR_A, CS0WCR_D
113 write32 CS5BCR_A, CS_USB_BCR_D
114 write32 CS5WCR_A, CS_USB_WCR_D
115 write32 CS6BCR_A, CS_SD_BCR_D
116 write32 CS6WCR_A, CS_SD_WCR_D
119 #if defined(CONFIG_SH_32BIT)
120 /*------- set PMB -------*/
121 write32 PASCR_A, PASCR_29BIT_D
122 write32 MMUCR_A, MMUCR_D
124 /*****************************************************************
125 * ent virt phys v sz c wt
126 * 0 0xa0000000 0x00000000 1 64M 0 0
127 * 1 0xa4000000 0x04000000 1 16M 0 0
128 * 2 0xa6000000 0x08000000 1 16M 0 0
129 * 9 0x88000000 0x48000000 1 128M 1 1
130 * 10 0x90000000 0x50000000 1 128M 1 1
131 * 11 0x98000000 0x58000000 1 128M 1 1
132 * 13 0xa8000000 0x48000000 1 128M 0 0
133 * 14 0xb0000000 0x50000000 1 128M 0 0
134 * 15 0xb8000000 0x58000000 1 128M 0 0
136 write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
137 write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
138 write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
139 write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
140 write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
141 write32 PMB_DATA_USB_A, PMB_DATA_USB_D
142 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
143 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
144 write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
145 write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
146 write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
147 write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
148 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
149 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
150 write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
151 write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
152 write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
153 write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
155 write32 PASCR_A, PASCR_INIT
167 /*------- GPIO -------*/
168 /* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
184 PPUPR1_D: .word 0xffbf
185 PPUPR2_D: .word 0xff00
186 P1MSELR_D: .word 0x3780
187 P2MSELR_D: .word 0x0000
189 #define GPIO_BASE 0xffe70000
190 PACR_A: .long GPIO_BASE + 0x00
191 PBCR_A: .long GPIO_BASE + 0x02
192 PCCR_A: .long GPIO_BASE + 0x04
193 PDCR_A: .long GPIO_BASE + 0x06
194 PECR_A: .long GPIO_BASE + 0x08
195 PFCR_A: .long GPIO_BASE + 0x0a
196 PGCR_A: .long GPIO_BASE + 0x0c
197 PHCR_A: .long GPIO_BASE + 0x0e
198 PJCR_A: .long GPIO_BASE + 0x10
199 PKCR_A: .long GPIO_BASE + 0x12
200 PLCR_A: .long GPIO_BASE + 0x14
201 PMCR_A: .long GPIO_BASE + 0x16
202 PNCR_A: .long GPIO_BASE + 0x18
203 PPCR_A: .long GPIO_BASE + 0x1a
204 PQCR_A: .long GPIO_BASE + 0x1c
205 PRCR_A: .long GPIO_BASE + 0x1e
206 PEPUPR_A: .long GPIO_BASE + 0x48
207 PHPUPR_A: .long GPIO_BASE + 0x4e
208 PJPUPR_A: .long GPIO_BASE + 0x50
209 PKPUPR_A: .long GPIO_BASE + 0x52
210 PLPUPR_A: .long GPIO_BASE + 0x54
211 PMPUPR_A: .long GPIO_BASE + 0x56
212 PNPUPR_A: .long GPIO_BASE + 0x58
213 PPUPR1_A: .long GPIO_BASE + 0x60
214 PPUPR2_A: .long GPIO_BASE + 0x62
215 P1MSELR_A: .long GPIO_BASE + 0x80
216 P2MSELR_A: .long GPIO_BASE + 0x82
218 MMSELR_A: .long 0xfc400020
219 #if defined(CONFIG_SH_32BIT)
220 MMSELR_D: .long 0xa5a50005
222 MMSELR_D: .long 0xa5a50002
225 /*------- DBSC2 -------*/
226 #define DBSC2_BASE 0xfe800000
227 DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
228 DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
229 DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
230 DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
231 DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
232 DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
233 DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
234 DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
235 DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
236 DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
237 DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
238 DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
239 DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
240 DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
241 DDR_DUMMY_ACCESS_A: .long 0x40000000
243 DBSC2_DBCONF_D: .long 0x00630002
244 DBSC2_DBTR0_D: .long 0x050b1f04
245 DBSC2_DBTR1_D: .long 0x00040204
246 DBSC2_DBTR2_D: .long 0x02100308
247 DBSC2_DBFREQ_D1: .long 0x00000000
248 DBSC2_DBFREQ_D2: .long 0x00000100
249 DBSC2_DBDICODTOCD_D:.long 0x000f0907
251 DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
252 DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
253 DBSC2_DBCMDCNT_D_REF: .long 0x00000004
255 DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
256 DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
257 DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
258 DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
259 DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
260 DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
262 DBSC2_DBEN_D: .long 0x00000001
264 DBSC2_DBPDCNT0_D3: .long 0x00000080
265 DBSC2_DBRFCNT1_D: .long 0x00000926
266 DBSC2_DBRFCNT2_D: .long 0x00fe00fe
267 DBSC2_DBRFCNT0_D: .long 0x00010000
269 WAIT_200US: .long 33333
271 /*------- LBSC -------*/
272 PASCR_A: .long 0xff000070
273 PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
276 CS0BCR_A: .long CS0BCR
277 CS0WCR_A: .long CS0WCR
278 CS1BCR_A: .long CS1BCR
279 CS1WCR_A: .long CS1WCR
280 CS2BCR_A: .long CS2BCR
281 CS2WCR_A: .long CS2WCR
282 CS3BCR_A: .long CS3BCR
283 CS3WCR_A: .long CS3WCR
284 CS4BCR_A: .long CS4BCR
285 CS4WCR_A: .long CS4WCR
286 CS5BCR_A: .long CS5BCR
287 CS5WCR_A: .long CS5WCR
288 CS6BCR_A: .long CS6BCR
289 CS6WCR_A: .long CS6WCR
291 BCR_D: .long 0x80000003
292 CS0BCR_D: .long 0x22222340
293 CS0WCR_D: .long 0x00111118
294 CS1BCR_D: .long 0x11111100
295 CS1WCR_D: .long 0x33333303
296 CS4BCR_D: .long 0x11111300
297 CS4WCR_D: .long 0x00101012
299 /* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
300 CS_USB_BCR_D: .long 0x11111200
301 CS_USB_WCR_D: .long 0x00020005
303 /* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
304 CS_SD_BCR_D: .long 0x00000300
305 CS_SD_WCR_D: .long 0x00030108
307 /* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
308 CS_I2C_BCR_D: .long 0x11111100
309 CS_I2C_WCR_D: .long 0x00000003
311 #if defined(CONFIG_SH_32BIT)
312 /*------- set PMB -------*/
313 PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
314 PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
315 PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
316 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
317 PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
318 PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
319 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
320 PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
321 PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
323 PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
324 PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
325 PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
326 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
327 PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
328 PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
329 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
330 PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
331 PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
333 PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
334 PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
335 PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
336 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
337 PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
338 PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
339 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
340 PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
341 PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
343 /* ppn ub v s1 s0 c wt */
344 PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
345 PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
346 PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
347 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
348 PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
349 PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
350 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
351 PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
352 PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
354 DUMMY_ADDR: .long 0xa0000000
355 PASCR_29BIT_D: .long 0x00000000
356 PASCR_INIT: .long 0x80000080 /* check booting mode */
357 MMUCR_A: .long 0xff000010
358 MMUCR_D: .long 0x00000004 /* clear ITLB */
359 #endif /* CONFIG_SH_32BIT */
361 CCR_A: .long 0xff00001c
362 CCR_D: .long 0x0000090b