2 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #include <asm/processor.h>
22 #include <asm/macro.h>
24 #include <asm/processor.h>
35 /*------- LBSC -------*/
36 write32 MMSELR_A, MMSELR_D
38 /*------- DBSC2 -------*/
39 write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
40 write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
41 write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
42 write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
43 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
44 write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
47 write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
48 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
50 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
51 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
52 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
53 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
54 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
55 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
56 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
57 write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
58 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
61 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
62 write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
64 write32 DBSC2_DBEN_A, DBSC2_DBEN_D
65 write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
66 write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
67 write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
70 /*------- GPIO -------*/
71 write16 PACR_A, PXCR_D
72 write16 PBCR_A, PXCR_D
73 write16 PCCR_A, PXCR_D
74 write16 PDCR_A, PXCR_D
75 write16 PECR_A, PXCR_D
76 write16 PFCR_A, PXCR_D
77 write16 PGCR_A, PXCR_D
78 write16 PHCR_A, PHCR_D
79 write16 PJCR_A, PJCR_D
80 write16 PKCR_A, PKCR_D
81 write16 PLCR_A, PXCR_D
82 write16 PMCR_A, PMCR_D
83 write16 PNCR_A, PNCR_D
84 write16 PPCR_A, PXCR_D
85 write16 PQCR_A, PXCR_D
86 write16 PRCR_A, PXCR_D
88 write8 PEPUPR_A, PEPUPR_D
89 write8 PHPUPR_A, PHPUPR_D
90 write8 PJPUPR_A, PJPUPR_D
91 write8 PKPUPR_A, PKPUPR_D
92 write8 PLPUPR_A, PLPUPR_D
93 write8 PMPUPR_A, PMPUPR_D
94 write8 PNPUPR_A, PNPUPR_D
95 write16 PPUPR1_A, PPUPR1_D
96 write16 PPUPR2_A, PPUPR2_D
97 write16 P1MSELR_A, P1MSELR_D
98 write16 P2MSELR_A, P2MSELR_D
100 /*------- LBSC -------*/
102 write32 CS0BCR_A, CS0BCR_D
103 write32 CS0WCR_A, CS0WCR_D
104 write32 CS1BCR_A, CS1BCR_D
105 write32 CS1WCR_A, CS1WCR_D
106 write32 CS4BCR_A, CS4BCR_D
107 write32 CS4WCR_A, CS4WCR_D
111 mov.l PASCR_32BIT_MODE, r1
115 write32 CS2BCR_A, CS_USB_BCR_D
116 write32 CS2WCR_A, CS_USB_WCR_D
117 write32 CS3BCR_A, CS_SD_BCR_D
118 write32 CS3WCR_A, CS_SD_WCR_D
119 write32 CS5BCR_A, CS_I2C_BCR_D
120 write32 CS5WCR_A, CS_I2C_WCR_D
121 write32 CS6BCR_A, CS0BCR_D
122 write32 CS6WCR_A, CS0WCR_D
127 write32 CS5BCR_A, CS_USB_BCR_D
128 write32 CS5WCR_A, CS_USB_WCR_D
129 write32 CS6BCR_A, CS_SD_BCR_D
130 write32 CS6WCR_A, CS_SD_WCR_D
133 #if defined(CONFIG_SH_32BIT)
134 /*------- set PMB -------*/
135 write32 PASCR_A, PASCR_29BIT_D
136 write32 MMUCR_A, MMUCR_D
138 /*****************************************************************
139 * ent virt phys v sz c wt
140 * 0 0xa0000000 0x00000000 1 64M 0 0
141 * 1 0xa4000000 0x04000000 1 16M 0 0
142 * 2 0xa6000000 0x08000000 1 16M 0 0
143 * 9 0x88000000 0x48000000 1 128M 1 1
144 * 10 0x90000000 0x50000000 1 128M 1 1
145 * 11 0x98000000 0x58000000 1 128M 1 1
146 * 13 0xa8000000 0x48000000 1 128M 0 0
147 * 14 0xb0000000 0x50000000 1 128M 0 0
148 * 15 0xb8000000 0x58000000 1 128M 0 0
150 write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
151 write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
152 write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
153 write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
154 write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
155 write32 PMB_DATA_USB_A, PMB_DATA_USB_D
156 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
157 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
158 write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
159 write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
160 write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
161 write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
162 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
163 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
164 write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
165 write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
166 write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
167 write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
169 write32 PASCR_A, PASCR_INIT
181 /*------- GPIO -------*/
182 /* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
198 PPUPR1_D: .word 0xffbf
199 PPUPR2_D: .word 0xff00
200 P1MSELR_D: .word 0x3780
201 P2MSELR_D: .word 0x0000
203 #define GPIO_BASE 0xffe70000
204 PACR_A: .long GPIO_BASE + 0x00
205 PBCR_A: .long GPIO_BASE + 0x02
206 PCCR_A: .long GPIO_BASE + 0x04
207 PDCR_A: .long GPIO_BASE + 0x06
208 PECR_A: .long GPIO_BASE + 0x08
209 PFCR_A: .long GPIO_BASE + 0x0a
210 PGCR_A: .long GPIO_BASE + 0x0c
211 PHCR_A: .long GPIO_BASE + 0x0e
212 PJCR_A: .long GPIO_BASE + 0x10
213 PKCR_A: .long GPIO_BASE + 0x12
214 PLCR_A: .long GPIO_BASE + 0x14
215 PMCR_A: .long GPIO_BASE + 0x16
216 PNCR_A: .long GPIO_BASE + 0x18
217 PPCR_A: .long GPIO_BASE + 0x1a
218 PQCR_A: .long GPIO_BASE + 0x1c
219 PRCR_A: .long GPIO_BASE + 0x1e
220 PEPUPR_A: .long GPIO_BASE + 0x48
221 PHPUPR_A: .long GPIO_BASE + 0x4e
222 PJPUPR_A: .long GPIO_BASE + 0x50
223 PKPUPR_A: .long GPIO_BASE + 0x52
224 PLPUPR_A: .long GPIO_BASE + 0x54
225 PMPUPR_A: .long GPIO_BASE + 0x56
226 PNPUPR_A: .long GPIO_BASE + 0x58
227 PPUPR1_A: .long GPIO_BASE + 0x60
228 PPUPR2_A: .long GPIO_BASE + 0x62
229 P1MSELR_A: .long GPIO_BASE + 0x80
230 P2MSELR_A: .long GPIO_BASE + 0x82
232 MMSELR_A: .long 0xfc400020
233 #if defined(CONFIG_SH_32BIT)
234 MMSELR_D: .long 0xa5a50005
236 MMSELR_D: .long 0xa5a50002
239 /*------- DBSC2 -------*/
240 #define DBSC2_BASE 0xfe800000
241 DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
242 DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
243 DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
244 DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
245 DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
246 DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
247 DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
248 DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
249 DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
250 DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
251 DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
252 DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
253 DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
254 DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
255 DDR_DUMMY_ACCESS_A: .long 0x40000000
257 DBSC2_DBCONF_D: .long 0x00630002
258 DBSC2_DBTR0_D: .long 0x050b1f04
259 DBSC2_DBTR1_D: .long 0x00040204
260 DBSC2_DBTR2_D: .long 0x02100308
261 DBSC2_DBFREQ_D1: .long 0x00000000
262 DBSC2_DBFREQ_D2: .long 0x00000100
263 DBSC2_DBDICODTOCD_D:.long 0x000f0907
265 DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
266 DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
267 DBSC2_DBCMDCNT_D_REF: .long 0x00000004
269 DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
270 DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
271 DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
272 DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
273 DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
274 DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
276 DBSC2_DBEN_D: .long 0x00000001
278 DBSC2_DBPDCNT0_D3: .long 0x00000080
279 DBSC2_DBRFCNT1_D: .long 0x00000926
280 DBSC2_DBRFCNT2_D: .long 0x00fe00fe
281 DBSC2_DBRFCNT0_D: .long 0x00010000
283 WAIT_200US: .long 33333
285 /*------- LBSC -------*/
286 PASCR_A: .long 0xff000070
287 PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
290 CS0BCR_A: .long CS0BCR
291 CS0WCR_A: .long CS0WCR
292 CS1BCR_A: .long CS1BCR
293 CS1WCR_A: .long CS1WCR
294 CS2BCR_A: .long CS2BCR
295 CS2WCR_A: .long CS2WCR
296 CS3BCR_A: .long CS3BCR
297 CS3WCR_A: .long CS3WCR
298 CS4BCR_A: .long CS4BCR
299 CS4WCR_A: .long CS4WCR
300 CS5BCR_A: .long CS5BCR
301 CS5WCR_A: .long CS5WCR
302 CS6BCR_A: .long CS6BCR
303 CS6WCR_A: .long CS6WCR
305 BCR_D: .long 0x80000003
306 CS0BCR_D: .long 0x22222340
307 CS0WCR_D: .long 0x00111118
308 CS1BCR_D: .long 0x11111100
309 CS1WCR_D: .long 0x33333303
310 CS4BCR_D: .long 0x11111300
311 CS4WCR_D: .long 0x00101012
313 /* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
314 CS_USB_BCR_D: .long 0x11111200
315 CS_USB_WCR_D: .long 0x00020005
317 /* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
318 CS_SD_BCR_D: .long 0x00000300
319 CS_SD_WCR_D: .long 0x00030108
321 /* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
322 CS_I2C_BCR_D: .long 0x11111100
323 CS_I2C_WCR_D: .long 0x00000003
325 #if defined(CONFIG_SH_32BIT)
326 /*------- set PMB -------*/
327 PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
328 PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
329 PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
330 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
331 PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
332 PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
333 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
334 PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
335 PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
337 PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
338 PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
339 PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
340 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
341 PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
342 PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
343 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
344 PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
345 PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
347 PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
348 PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
349 PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
350 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
351 PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
352 PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
353 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
354 PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
355 PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
357 /* ppn ub v s1 s0 c wt */
358 PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
359 PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
360 PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
361 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
362 PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
363 PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
364 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
365 PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
366 PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
368 DUMMY_ADDR: .long 0xa0000000
369 PASCR_29BIT_D: .long 0x00000000
370 PASCR_INIT: .long 0x80000080 /* check booting mode */
371 MMUCR_A: .long 0xff000010
372 MMUCR_D: .long 0x00000004 /* clear ITLB */
373 #endif /* CONFIG_SH_32BIT */
375 CCR_A: .long 0xff00001c
376 CCR_D: .long 0x0000090b