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[u-boot] / board / ronetix / pm9261 / pm9261.c
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian.pop@leadtechdesign.com>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6  * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 #include <common.h>
28 #include <asm/sizes.h>
29 #include <asm/arch/at91sam9261.h>
30 #include <asm/arch/at91sam9_smc.h>
31 #include <asm/arch/at91_common.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_rstc.h>
34 #include <asm/arch/at91_matrix.h>
35 #include <asm/arch/at91_pio.h>
36 #include <asm/arch/clk.h>
37 #include <asm/arch/at91_pio.h>
38 #include <asm/arch/io.h>
39 #include <asm/arch/hardware.h>
40 #include <lcd.h>
41 #include <atmel_lcdc.h>
42 #include <dataflash.h>
43 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
44 #include <net.h>
45 #endif
46 #include <netdev.h>
47
48 DECLARE_GLOBAL_DATA_PTR;
49
50 /* ------------------------------------------------------------------------- */
51 /*
52  * Miscelaneous platform dependent initialisations
53  */
54
55 #ifdef CONFIG_CMD_NAND
56 static void pm9261_nand_hw_init(void)
57 {
58         unsigned long csa;
59         at91_smc_t      *smc    = (at91_smc_t *) AT91_SMC_BASE;
60         at91_matrix_t   *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
61         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
62
63         /* Enable CS3 */
64         csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
65         writel(csa, &matrix->csa);
66
67         /* Configure SMC CS3 for NAND/SmartMedia */
68         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
69                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
70                 &smc->cs[3].setup);
71
72         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
73                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
74                 &smc->cs[3].pulse);
75
76         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
77                 &smc->cs[3].cycle);
78
79         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
80                 AT91_SMC_MODE_EXNW_DISABLE |
81 #ifdef CONFIG_SYS_NAND_DBW_16
82                 AT91_SMC_MODE_DBW_16 |
83 #else /* CONFIG_SYS_NAND_DBW_8 */
84                 AT91_SMC_MODE_DBW_8 |
85 #endif
86                 AT91_SMC_MODE_TDF_CYCLE(2),
87                 &smc->cs[3].mode);
88
89         writel(1 << AT91SAM9261_ID_PIOA |
90                 1 << AT91SAM9261_ID_PIOC,
91                 &pmc->pcer);
92
93         /* Configure RDY/BSY */
94         at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
95
96         /* Enable NandFlash */
97         at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
98
99         at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* NANDOE */
100         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* NANDWE */
101 }
102 #endif
103
104
105 #ifdef CONFIG_DRIVER_DM9000
106 static void pm9261_dm9000_hw_init(void)
107 {
108         at91_smc_t      *smc    = (at91_smc_t *) AT91_SMC_BASE;
109         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
110
111         /* Configure SMC CS2 for DM9000 */
112         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
113                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
114                 &smc->cs[2].setup);
115
116         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
117                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
118                 &smc->cs[2].pulse);
119
120         writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
121                 &smc->cs[2].cycle);
122
123         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
124                 AT91_SMC_MODE_EXNW_DISABLE |
125                 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
126                 AT91_SMC_MODE_TDF_CYCLE(1),
127                 &smc->cs[2].mode);
128
129         /* Configure Interrupt pin as input, no pull-up */
130         writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer);
131         at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
132 }
133 #endif
134
135 #ifdef CONFIG_LCD
136 vidinfo_t panel_info = {
137         vl_col:         240,
138         vl_row:         320,
139         vl_clk:         4965000,
140         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
141                         ATMEL_LCDC_INVFRAME_INVERTED,
142         vl_bpix:        3,
143         vl_tft:         1,
144         vl_hsync_len:   5,
145         vl_left_margin: 1,
146         vl_right_margin:33,
147         vl_vsync_len:   1,
148         vl_upper_margin:1,
149         vl_lower_margin:0,
150         mmio:           AT91SAM9261_LCDC_BASE,
151 };
152
153 void lcd_enable(void)
154 {
155         at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
156 }
157
158 void lcd_disable(void)
159 {
160         at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
161 }
162
163 static void pm9261_lcd_hw_init(void)
164 {
165         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
166
167         at91_set_a_periph(AT91_PIO_PORTB, 1, 0);        /* LCDHSYNC */
168         at91_set_a_periph(AT91_PIO_PORTB, 2, 0);        /* LCDDOTCK */
169         at91_set_a_periph(AT91_PIO_PORTB, 3, 0);        /* LCDDEN */
170         at91_set_a_periph(AT91_PIO_PORTB, 4, 0);        /* LCDCC */
171         at91_set_a_periph(AT91_PIO_PORTB, 7, 0);        /* LCDD2 */
172         at91_set_a_periph(AT91_PIO_PORTB, 8, 0);        /* LCDD3 */
173         at91_set_a_periph(AT91_PIO_PORTB, 9, 0);        /* LCDD4 */
174         at91_set_a_periph(AT91_PIO_PORTB, 10, 0);       /* LCDD5 */
175         at91_set_a_periph(AT91_PIO_PORTB, 11, 0);       /* LCDD6 */
176         at91_set_a_periph(AT91_PIO_PORTB, 12, 0);       /* LCDD7 */
177         at91_set_a_periph(AT91_PIO_PORTB, 15, 0);       /* LCDD10 */
178         at91_set_a_periph(AT91_PIO_PORTB, 16, 0);       /* LCDD11 */
179         at91_set_a_periph(AT91_PIO_PORTB, 17, 0);       /* LCDD12 */
180         at91_set_a_periph(AT91_PIO_PORTB, 18, 0);       /* LCDD13 */
181         at91_set_a_periph(AT91_PIO_PORTB, 19, 0);       /* LCDD14 */
182         at91_set_a_periph(AT91_PIO_PORTB, 20, 0);       /* LCDD15 */
183         at91_set_b_periph(AT91_PIO_PORTB, 23, 0);       /* LCDD18 */
184         at91_set_b_periph(AT91_PIO_PORTB, 24, 0);       /* LCDD19 */
185         at91_set_b_periph(AT91_PIO_PORTB, 25, 0);       /* LCDD20 */
186         at91_set_b_periph(AT91_PIO_PORTB, 26, 0);       /* LCDD21 */
187         at91_set_b_periph(AT91_PIO_PORTB, 27, 0);       /* LCDD22 */
188         at91_set_b_periph(AT91_PIO_PORTB, 28, 0);       /* LCDD23 */
189
190         writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
191
192         gd->fb_base = AT91SAM9261_SRAM_BASE;
193 }
194
195 #ifdef CONFIG_LCD_INFO
196 #include <nand.h>
197 #include <version.h>
198
199 extern flash_info_t flash_info[];
200
201 void lcd_show_board_info(void)
202 {
203         ulong dram_size, nand_size, flash_size, dataflash_size;
204         int i;
205         char temp[32];
206
207         lcd_printf ("%s\n", U_BOOT_VERSION);
208         lcd_printf ("(C) 2009 Ronetix GmbH\n");
209         lcd_printf ("support@ronetix.at\n");
210         lcd_printf ("%s CPU at %s MHz",
211                 CONFIG_SYS_AT91_CPU_NAME,
212                 strmhz(temp, get_cpu_clk_rate()));
213
214         dram_size = 0;
215         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
216                 dram_size += gd->bd->bi_dram[i].size;
217
218         nand_size = 0;
219         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
220                 nand_size += nand_info[i].size;
221
222         flash_size = 0;
223         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
224                 flash_size += flash_info[i].size;
225
226         dataflash_size = 0;
227         for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
228                 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
229                                 dataflash_info[i].Device.pages_size;
230
231         lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
232                         "%ld MB DataFlash\n",
233                 dram_size >> 20,
234                 nand_size >> 20,
235                 flash_size >> 20,
236                 dataflash_size >> 20);
237 }
238 #endif /* CONFIG_LCD_INFO */
239
240 #endif /* CONFIG_LCD */
241
242 int board_init(void)
243 {
244         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
245
246         /* Enable Ctrlc */
247         console_init_f();
248
249         writel(1 << AT91SAM9261_ID_PIOA |
250                 1 << AT91SAM9261_ID_PIOC,
251                 &pmc->pcer);
252
253         /* arch number of PM9261-Board */
254         gd->bd->bi_arch_number = MACH_TYPE_PM9261;
255
256         /* adress of boot parameters */
257         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
258
259         at91_serial_hw_init();
260 #ifdef CONFIG_CMD_NAND
261         pm9261_nand_hw_init();
262 #endif
263 #ifdef CONFIG_HAS_DATAFLASH
264         at91_spi0_hw_init(1 << 0);
265 #endif
266 #ifdef CONFIG_DRIVER_DM9000
267         pm9261_dm9000_hw_init();
268 #endif
269 #ifdef CONFIG_LCD
270         pm9261_lcd_hw_init();
271 #endif
272         return 0;
273 }
274
275 #ifdef CONFIG_DRIVER_DM9000
276 int board_eth_init(bd_t *bis)
277 {
278         return dm9000_initialize(bis);
279 }
280 #endif
281
282 int dram_init(void)
283 {
284         gd->bd->bi_dram[0].start = PHYS_SDRAM;
285         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
286         return 0;
287 }
288
289 #ifdef CONFIG_RESET_PHY_R
290 void reset_phy(void)
291 {
292 #ifdef CONFIG_DRIVER_DM9000
293         /*
294          * Initialize ethernet HW addr prior to starting Linux,
295          * needed for nfsroot
296          */
297         eth_init(gd->bd);
298 #endif
299 }
300 #endif
301
302 #ifdef CONFIG_DISPLAY_BOARDINFO
303 int checkboard (void)
304 {
305         char buf[32];
306
307         printf ("Board : Ronetix PM9261\n");
308         printf ("Crystal frequency: %8s MHz\n",
309                                         strmhz(buf, get_main_clk_rate()));
310         printf ("CPU clock        : %8s MHz\n",
311                                         strmhz(buf, get_cpu_clk_rate()));
312         printf ("Master clock     : %8s MHz\n",
313                                         strmhz(buf, get_mck_clk_rate()));
314
315         return 0;
316 }
317 #endif