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[u-boot] / board / ronetix / pm9261 / pm9261.c
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian.pop@leadtechdesign.com>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6  * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 #include <common.h>
28 #include <asm/sizes.h>
29 #include <asm/arch/at91sam9261.h>
30 #include <asm/arch/at91sam9261_matrix.h>
31 #include <asm/arch/at91sam9_smc.h>
32 #include <asm/arch/at91_common.h>
33 #include <asm/arch/at91_pmc.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/clk.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/io.h>
38 #include <asm/arch/hardware.h>
39 #include <lcd.h>
40 #include <atmel_lcdc.h>
41 #include <dataflash.h>
42 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
43 #include <net.h>
44 #endif
45 #include <netdev.h>
46
47 DECLARE_GLOBAL_DATA_PTR;
48
49 /* ------------------------------------------------------------------------- */
50 /*
51  * Miscelaneous platform dependent initialisations
52  */
53
54 #ifdef CONFIG_CMD_NAND
55 static void pm9261_nand_hw_init(void)
56 {
57         unsigned long csa;
58
59         /* Enable CS3 */
60         csa = at91_sys_read(AT91_MATRIX_EBICSA);
61         at91_sys_write(AT91_MATRIX_EBICSA,
62                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
63
64         /* Configure SMC CS3 for NAND/SmartMedia */
65         at91_sys_write(AT91_SMC_SETUP(3),
66                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
67                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
68         at91_sys_write(AT91_SMC_PULSE(3),
69                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
70                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
71         at91_sys_write(AT91_SMC_CYCLE(3),
72                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
73         at91_sys_write(AT91_SMC_MODE(3),
74                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
75                        AT91_SMC_EXNWMODE_DISABLE |
76 #ifdef CONFIG_SYS_NAND_DBW_16
77                        AT91_SMC_DBW_16 |
78 #else /* CONFIG_SYS_NAND_DBW_8 */
79                        AT91_SMC_DBW_8 |
80 #endif
81                        AT91_SMC_TDF_(2));
82
83         /* Configure RDY/BSY */
84         at91_set_gpio_input(AT91_PIN_PA16, 1);
85
86         /* Enable NandFlash */
87         at91_set_gpio_output(AT91_PIN_PC14, 1);
88
89         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
90         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
91 }
92 #endif
93
94
95 #ifdef CONFIG_DRIVER_DM9000
96 static void pm9261_dm9000_hw_init(void)
97 {
98         /* Configure SMC CS2 for DM9000 */
99         at91_sys_write(AT91_SMC_SETUP(2),
100                        AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
101                        AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
102         at91_sys_write(AT91_SMC_PULSE(2),
103                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
104                        AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
105         at91_sys_write(AT91_SMC_CYCLE(2),
106                        AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
107         at91_sys_write(AT91_SMC_MODE(2),
108                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
109                        AT91_SMC_EXNWMODE_DISABLE |
110                        AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
111                        AT91_SMC_TDF_(1));
112
113         /* Configure Interrupt pin as input, no pull-up */
114         at91_set_gpio_input(AT91_PIN_PA24, 0);
115 }
116 #endif
117
118 #ifdef CONFIG_LCD
119 vidinfo_t panel_info = {
120         vl_col:         240,
121         vl_row:         320,
122         vl_clk:         4965000,
123         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
124                         ATMEL_LCDC_INVFRAME_INVERTED,
125         vl_bpix:        3,
126         vl_tft:         1,
127         vl_hsync_len:   5,
128         vl_left_margin: 1,
129         vl_right_margin:33,
130         vl_vsync_len:   1,
131         vl_upper_margin:1,
132         vl_lower_margin:0,
133         mmio:           AT91SAM9261_LCDC_BASE,
134 };
135
136 void lcd_enable(void)
137 {
138         at91_set_gpio_value(AT91_PIN_PA22, 0);  /* power up */
139 }
140
141 void lcd_disable(void)
142 {
143         at91_set_gpio_value(AT91_PIN_PA22, 1);  /* power down */
144 }
145
146 static void pm9261_lcd_hw_init(void)
147 {
148         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
149         at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
150         at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
151         at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
152         at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
153         at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
154         at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
155         at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
156         at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
157         at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
158         at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
159         at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
160         at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
161         at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
162         at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
163         at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
164         at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
165         at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
166         at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
167         at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
168         at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
169         at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
170
171         at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
172
173         gd->fb_base = AT91SAM9261_SRAM_BASE;
174 }
175
176 #ifdef CONFIG_LCD_INFO
177 #include <nand.h>
178 #include <version.h>
179
180 extern flash_info_t flash_info[];
181
182 void lcd_show_board_info(void)
183 {
184         ulong dram_size, nand_size, flash_size, dataflash_size;
185         int i;
186         char temp[32];
187
188         lcd_printf ("%s\n", U_BOOT_VERSION);
189         lcd_printf ("(C) 2009 Ronetix GmbH\n");
190         lcd_printf ("support@ronetix.at\n");
191         lcd_printf ("%s CPU at %s MHz",
192                 AT91_CPU_NAME,
193                 strmhz(temp, get_cpu_clk_rate()));
194
195         dram_size = 0;
196         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
197                 dram_size += gd->bd->bi_dram[i].size;
198
199         nand_size = 0;
200         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
201                 nand_size += nand_info[i].size;
202
203         flash_size = 0;
204         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
205                 flash_size += flash_info[i].size;
206
207         dataflash_size = 0;
208         for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
209                 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
210                                 dataflash_info[i].Device.pages_size;
211
212         lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
213                         "%ld MB DataFlash\n",
214                 dram_size >> 20,
215                 nand_size >> 20,
216                 flash_size >> 20,
217                 dataflash_size >> 20);
218 }
219 #endif /* CONFIG_LCD_INFO */
220
221 #endif /* CONFIG_LCD */
222
223 int board_init(void)
224 {
225         /* Enable Ctrlc */
226         console_init_f();
227
228         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
229         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
230
231         /* arch number of PM9261-Board */
232         gd->bd->bi_arch_number = MACH_TYPE_PM9261;
233
234         /* adress of boot parameters */
235         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
236
237         at91_serial_hw_init();
238 #ifdef CONFIG_CMD_NAND
239         pm9261_nand_hw_init();
240 #endif
241 #ifdef CONFIG_HAS_DATAFLASH
242         at91_spi0_hw_init(1 << 0);
243 #endif
244 #ifdef CONFIG_DRIVER_DM9000
245         pm9261_dm9000_hw_init();
246 #endif
247 #ifdef CONFIG_LCD
248         pm9261_lcd_hw_init();
249 #endif
250         return 0;
251 }
252
253 int dram_init(void)
254 {
255         gd->bd->bi_dram[0].start = PHYS_SDRAM;
256         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
257         return 0;
258 }
259
260 #ifdef CONFIG_RESET_PHY_R
261 void reset_phy(void)
262 {
263 #ifdef CONFIG_DRIVER_DM9000
264         /*
265          * Initialize ethernet HW addr prior to starting Linux,
266          * needed for nfsroot
267          */
268         eth_init(gd->bd);
269 #endif
270 }
271 #endif
272
273 #ifdef CONFIG_DISPLAY_BOARDINFO
274 int checkboard (void)
275 {
276         char buf[32];
277
278         printf ("Board : Ronetix PM9261\n");
279         printf ("Crystal frequency: %8s MHz\n",
280                                         strmhz(buf, get_main_clk_rate()));
281         printf ("CPU clock        : %8s MHz\n",
282                                         strmhz(buf, get_cpu_clk_rate()));
283         printf ("Master clock     : %8s MHz\n",
284                                         strmhz(buf, get_mck_clk_rate()));
285
286         return 0;
287 }
288 #endif