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1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6  * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <linux/sizes.h>
13 #include <asm/io.h>
14 #include <asm/gpio.h>
15 #include <asm/arch/at91sam9_smc.h>
16 #include <asm/arch/at91_common.h>
17 #include <asm/arch/at91_rstc.h>
18 #include <asm/arch/at91_matrix.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/gpio.h>
21
22 #include <lcd.h>
23 #include <atmel_lcdc.h>
24 #include <dataflash.h>
25 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
26 #include <net.h>
27 #endif
28 #include <netdev.h>
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 /* ------------------------------------------------------------------------- */
33 /*
34  * Miscelaneous platform dependent initialisations
35  */
36
37 #ifdef CONFIG_CMD_NAND
38 static void pm9261_nand_hw_init(void)
39 {
40         unsigned long csa;
41         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
42         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
43
44         /* Enable CS3 */
45         csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
46         writel(csa, &matrix->csa);
47
48         /* Configure SMC CS3 for NAND/SmartMedia */
49         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
50                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
51                 &smc->cs[3].setup);
52
53         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
54                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
55                 &smc->cs[3].pulse);
56
57         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
58                 &smc->cs[3].cycle);
59
60         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
61                 AT91_SMC_MODE_EXNW_DISABLE |
62 #ifdef CONFIG_SYS_NAND_DBW_16
63                 AT91_SMC_MODE_DBW_16 |
64 #else /* CONFIG_SYS_NAND_DBW_8 */
65                 AT91_SMC_MODE_DBW_8 |
66 #endif
67                 AT91_SMC_MODE_TDF_CYCLE(2),
68                 &smc->cs[3].mode);
69
70         at91_periph_clk_enable(ATMEL_ID_PIOA);
71         at91_periph_clk_enable(ATMEL_ID_PIOC);
72
73         /* Configure RDY/BSY */
74         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
75
76         /* Enable NandFlash */
77         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
78
79         at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* NANDOE */
80         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* NANDWE */
81 }
82 #endif
83
84
85 #ifdef CONFIG_DRIVER_DM9000
86 static void pm9261_dm9000_hw_init(void)
87 {
88         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
89
90         /* Configure SMC CS2 for DM9000 */
91         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
92                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
93                 &smc->cs[2].setup);
94
95         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
96                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
97                 &smc->cs[2].pulse);
98
99         writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
100                 &smc->cs[2].cycle);
101
102         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
103                 AT91_SMC_MODE_EXNW_DISABLE |
104                 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
105                 AT91_SMC_MODE_TDF_CYCLE(1),
106                 &smc->cs[2].mode);
107
108         /* Configure Interrupt pin as input, no pull-up */
109         at91_periph_clk_enable(ATMEL_ID_PIOA);
110         at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
111 }
112 #endif
113
114 #ifdef CONFIG_LCD
115 vidinfo_t panel_info = {
116         .vl_col =               240,
117         .vl_row =               320,
118         .vl_clk =               4965000,
119         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
120                                 ATMEL_LCDC_INVFRAME_INVERTED,
121         .vl_bpix =              3,
122         .vl_tft =               1,
123         .vl_hsync_len =         5,
124         .vl_left_margin =       1,
125         .vl_right_margin =      33,
126         .vl_vsync_len =         1,
127         .vl_upper_margin =      1,
128         .vl_lower_margin =      0,
129         .mmio =                 ATMEL_BASE_LCDC,
130 };
131
132 void lcd_enable(void)
133 {
134         at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
135 }
136
137 void lcd_disable(void)
138 {
139         at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
140 }
141
142 static void pm9261_lcd_hw_init(void)
143 {
144         at91_set_a_periph(AT91_PIO_PORTB, 1, 0);        /* LCDHSYNC */
145         at91_set_a_periph(AT91_PIO_PORTB, 2, 0);        /* LCDDOTCK */
146         at91_set_a_periph(AT91_PIO_PORTB, 3, 0);        /* LCDDEN */
147         at91_set_a_periph(AT91_PIO_PORTB, 4, 0);        /* LCDCC */
148         at91_set_a_periph(AT91_PIO_PORTB, 7, 0);        /* LCDD2 */
149         at91_set_a_periph(AT91_PIO_PORTB, 8, 0);        /* LCDD3 */
150         at91_set_a_periph(AT91_PIO_PORTB, 9, 0);        /* LCDD4 */
151         at91_set_a_periph(AT91_PIO_PORTB, 10, 0);       /* LCDD5 */
152         at91_set_a_periph(AT91_PIO_PORTB, 11, 0);       /* LCDD6 */
153         at91_set_a_periph(AT91_PIO_PORTB, 12, 0);       /* LCDD7 */
154         at91_set_a_periph(AT91_PIO_PORTB, 15, 0);       /* LCDD10 */
155         at91_set_a_periph(AT91_PIO_PORTB, 16, 0);       /* LCDD11 */
156         at91_set_a_periph(AT91_PIO_PORTB, 17, 0);       /* LCDD12 */
157         at91_set_a_periph(AT91_PIO_PORTB, 18, 0);       /* LCDD13 */
158         at91_set_a_periph(AT91_PIO_PORTB, 19, 0);       /* LCDD14 */
159         at91_set_a_periph(AT91_PIO_PORTB, 20, 0);       /* LCDD15 */
160         at91_set_b_periph(AT91_PIO_PORTB, 23, 0);       /* LCDD18 */
161         at91_set_b_periph(AT91_PIO_PORTB, 24, 0);       /* LCDD19 */
162         at91_set_b_periph(AT91_PIO_PORTB, 25, 0);       /* LCDD20 */
163         at91_set_b_periph(AT91_PIO_PORTB, 26, 0);       /* LCDD21 */
164         at91_set_b_periph(AT91_PIO_PORTB, 27, 0);       /* LCDD22 */
165         at91_set_b_periph(AT91_PIO_PORTB, 28, 0);       /* LCDD23 */
166
167         at91_system_clk_enable(AT91_PMC_HCK1);
168
169         gd->fb_base = ATMEL_BASE_SRAM;
170 }
171
172 #ifdef CONFIG_LCD_INFO
173 #include <nand.h>
174 #include <version.h>
175
176 extern flash_info_t flash_info[];
177
178 void lcd_show_board_info(void)
179 {
180         ulong dram_size, nand_size, flash_size, dataflash_size;
181         int i;
182         char temp[32];
183
184         lcd_printf ("%s\n", U_BOOT_VERSION);
185         lcd_printf ("(C) 2009 Ronetix GmbH\n");
186         lcd_printf ("support@ronetix.at\n");
187         lcd_printf ("%s CPU at %s MHz",
188                 CONFIG_SYS_AT91_CPU_NAME,
189                 strmhz(temp, get_cpu_clk_rate()));
190
191         dram_size = 0;
192         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
193                 dram_size += gd->bd->bi_dram[i].size;
194
195         nand_size = 0;
196         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
197                 nand_size += nand_info[i]->size;
198
199         flash_size = 0;
200         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
201                 flash_size += flash_info[i].size;
202
203         dataflash_size = 0;
204         for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
205                 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
206                                 dataflash_info[i].Device.pages_size;
207
208         lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
209                         "%ld MB DataFlash\n",
210                 dram_size >> 20,
211                 nand_size >> 20,
212                 flash_size >> 20,
213                 dataflash_size >> 20);
214 }
215 #endif /* CONFIG_LCD_INFO */
216
217 #endif /* CONFIG_LCD */
218
219 int board_early_init_f(void)
220 {
221         at91_periph_clk_enable(ATMEL_ID_PIOA);
222         at91_periph_clk_enable(ATMEL_ID_PIOC);
223
224         at91_seriald_hw_init();
225
226         return 0;
227 }
228
229 int board_init(void)
230 {
231         /* arch number of PM9261-Board */
232         gd->bd->bi_arch_number = MACH_TYPE_PM9261;
233
234         /* adress of boot parameters */
235         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
236
237 #ifdef CONFIG_CMD_NAND
238         pm9261_nand_hw_init();
239 #endif
240 #ifdef CONFIG_HAS_DATAFLASH
241         at91_spi0_hw_init(1 << 0);
242 #endif
243 #ifdef CONFIG_DRIVER_DM9000
244         pm9261_dm9000_hw_init();
245 #endif
246 #ifdef CONFIG_LCD
247         pm9261_lcd_hw_init();
248 #endif
249         return 0;
250 }
251
252 #ifdef CONFIG_DRIVER_DM9000
253 int board_eth_init(bd_t *bis)
254 {
255         return dm9000_initialize(bis);
256 }
257 #endif
258
259 int dram_init(void)
260 {
261         /* dram_init must store complete ramsize in gd->ram_size */
262         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
263                                 PHYS_SDRAM_SIZE);
264         return 0;
265 }
266
267 void dram_init_banksize(void)
268 {
269         gd->bd->bi_dram[0].start = PHYS_SDRAM;
270         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
271 }
272
273 #ifdef CONFIG_RESET_PHY_R
274 void reset_phy(void)
275 {
276 #ifdef CONFIG_DRIVER_DM9000
277         /*
278          * Initialize ethernet HW addr prior to starting Linux,
279          * needed for nfsroot
280          */
281         eth_init();
282 #endif
283 }
284 #endif
285
286 #ifdef CONFIG_DISPLAY_BOARDINFO
287 int checkboard (void)
288 {
289         char buf[32];
290
291         printf ("Board : Ronetix PM9261\n");
292         printf ("Crystal frequency: %8s MHz\n",
293                                         strmhz(buf, get_main_clk_rate()));
294         printf ("CPU clock        : %8s MHz\n",
295                                         strmhz(buf, get_cpu_clk_rate()));
296         printf ("Master clock     : %8s MHz\n",
297                                         strmhz(buf, get_mck_clk_rate()));
298
299         return 0;
300 }
301 #endif