2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/sizes.h>
15 #include <asm/arch/at91sam9_smc.h>
16 #include <asm/arch/at91_common.h>
17 #include <asm/arch/at91_rstc.h>
18 #include <asm/arch/at91_matrix.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/gpio.h>
22 #include <atmel_lcdc.h>
23 #include <dataflash.h>
24 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
29 DECLARE_GLOBAL_DATA_PTR;
31 /* ------------------------------------------------------------------------- */
33 * Miscelaneous platform dependent initialisations
36 #ifdef CONFIG_CMD_NAND
37 static void pm9263_nand_hw_init(void)
40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
44 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
45 writel(csa, &matrix->csa[0]);
47 /* Configure SMC CS3 for NAND/SmartMedia */
48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61 #ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 |
63 #else /* CONFIG_SYS_NAND_DBW_8 */
66 AT91_SMC_MODE_TDF_CYCLE(2),
69 /* Configure RDY/BSY */
70 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
72 /* Enable NandFlash */
73 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
78 static void pm9263_macb_hw_init(void)
81 * PB27 enables the 50MHz oscillator for Ethernet PHY
85 at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
86 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
88 at91_periph_clk_enable(ATMEL_ID_EMAC);
92 * RXDV (PC25) => PHY normal mode (not Test mode)
93 * ERX0 (PE25) => PHY ADDR0
94 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
96 * PHY has internal pull-down
99 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
100 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
101 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
103 /* Re-enable pull-up */
104 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
105 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
106 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
113 vidinfo_t panel_info = {
117 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
118 ATMEL_LCDC_INVFRAME_INVERTED,
123 .vl_right_margin = 33,
125 .vl_upper_margin = 1,
126 .vl_lower_margin = 0,
127 .mmio = ATMEL_BASE_LCDC,
130 void lcd_enable(void)
132 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
135 void lcd_disable(void)
137 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
140 #ifdef CONFIG_LCD_IN_PSRAM
142 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
143 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
145 /* Initialize the PSRAM memory */
146 static int pm9263_lcd_hw_psram_init(void)
149 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
150 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
152 /* Enable CS3 3.3v, no pull-ups */
153 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
154 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
156 writel(csa, &matrix->csa[1]);
158 /* Configure SMC1 CS0 for PSRAM - 16-bit */
159 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
160 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
163 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
164 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
167 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
170 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
173 /* setup PB29 as output */
174 at91_set_pio_output(PSRAM_CRE_PIN, 1);
176 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
178 /* PSRAM: write BCR */
179 readw(PSRAM_CTRL_REG);
180 readw(PSRAM_CTRL_REG);
181 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
182 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
184 /* write RCR of the PSRAM */
185 readw(PSRAM_CTRL_REG);
186 readw(PSRAM_CTRL_REG);
187 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
188 /* set RCR; 0x10-async mode,0x90-page mode */
189 writew(0x90, PSRAM_CTRL_REG);
192 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
193 * MT45W2M16B - CRE must be 0
194 * MT45W2M16A - CRE must be 1
196 writew(0x1234, PHYS_PSRAM);
197 writew(0x5678, PHYS_PSRAM + 2);
199 /* test if the chip is MT45W2M16B */
200 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
201 /* try with CRE=1 (MT45W2M16A) */
202 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
204 /* write RCR of the PSRAM */
205 readw(PSRAM_CTRL_REG);
206 readw(PSRAM_CTRL_REG);
207 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
208 /* set RCR;0x10-async mode,0x90-page mode */
209 writew(0x90, PSRAM_CTRL_REG);
212 writew(0x1234, PHYS_PSRAM);
213 writew(0x5678, PHYS_PSRAM+2);
214 if ((readw(PHYS_PSRAM) != 0x1234)
215 || (readw(PHYS_PSRAM + 2) != 0x5678))
221 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
222 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
228 static void pm9263_lcd_hw_init(void)
230 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
231 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
232 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
233 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
234 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
235 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
236 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
237 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
238 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
239 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
240 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
241 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
242 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
243 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
244 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
245 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
246 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
247 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
248 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
249 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
250 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
251 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
252 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
254 at91_periph_clk_enable(ATMEL_ID_LCDC);
257 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
258 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
260 #ifdef CONFIG_LCD_IN_PSRAM
261 /* initialize te PSRAM */
262 int stat = pm9263_lcd_hw_psram_init();
264 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
266 gd->fb_base = ATMEL_BASE_SRAM0;
271 #ifdef CONFIG_LCD_INFO
275 extern flash_info_t flash_info[];
277 void lcd_show_board_info(void)
279 ulong dram_size, nand_size, flash_size, dataflash_size;
283 lcd_printf ("%s\n", U_BOOT_VERSION);
284 lcd_printf ("(C) 2009 Ronetix GmbH\n");
285 lcd_printf ("support@ronetix.at\n");
286 lcd_printf ("%s CPU at %s MHz",
287 CONFIG_SYS_AT91_CPU_NAME,
288 strmhz(temp, get_cpu_clk_rate()));
291 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
292 dram_size += gd->bd->bi_dram[i].size;
295 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
296 nand_size += nand_info[i]->size;
299 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
300 flash_size += flash_info[i].size;
303 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
304 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
305 dataflash_info[i].Device.pages_size;
307 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
308 "4 MB PSRAM, %ld MB DataFlash\n",
312 dataflash_size >> 20);
314 #endif /* CONFIG_LCD_INFO */
316 #endif /* CONFIG_LCD */
318 int board_early_init_f(void)
320 at91_periph_clk_enable(ATMEL_ID_PIOA);
321 at91_periph_clk_enable(ATMEL_ID_PIOB);
322 at91_periph_clk_enable(ATMEL_ID_PIOCDE);
324 at91_seriald_hw_init();
331 /* arch number of AT91SAM9263EK-Board */
332 gd->bd->bi_arch_number = MACH_TYPE_PM9263;
334 /* adress of boot parameters */
335 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
337 #ifdef CONFIG_CMD_NAND
338 pm9263_nand_hw_init();
340 #ifdef CONFIG_HAS_DATAFLASH
341 at91_spi0_hw_init(1 << 0);
344 pm9263_macb_hw_init();
346 #ifdef CONFIG_USB_OHCI_NEW
350 pm9263_lcd_hw_init();
357 /* dram_init must store complete ramsize in gd->ram_size */
358 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
363 void dram_init_banksize(void)
365 gd->bd->bi_dram[0].start = PHYS_SDRAM;
366 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
369 #ifdef CONFIG_RESET_PHY_R
375 int board_eth_init(bd_t *bis)
379 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
384 #ifdef CONFIG_DISPLAY_BOARDINFO
385 int checkboard (void)
389 printf ("Board : Ronetix PM9263\n");
391 switch (gd->fb_base) {
396 case ATMEL_BASE_SRAM0:
397 ss = "(Internal SRAM)";
404 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );