3 * Custom IDEAS, Inc. <www.cideas.com>
4 * Gerald Van Baren <vanbaren@cideas.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/u-boot.h>
29 /*NO// #include <memtest.h> */
33 #ifdef CONFIG_SHOW_BOOT_PROGRESS
34 #include <status_led.h>
38 #include "ioconfig.h" /* I/O configuration table */
41 * PBI Page Based Interleaving
42 * PSDMR_PBI page based interleaving
43 * 0 bank based interleaving
44 * External Address Multiplexing (EAMUX) adds a clock to address cycles
45 * (this can help with marginal board layouts)
46 * PSDMR_EAMUX adds a clock
48 * Buffer Command (BUFCMD) adds a clock to command cycles.
49 * PSDMR_BUFCMD adds a clock
52 #define CONFIG_PBI PSDMR_PBI
53 #define PESSIMISTIC_SDRAM 0
54 #define EAMUX 0 /* EST requires EAMUX */
60 #define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */
61 #define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */
62 #define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */
63 #define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */
64 #define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */
69 #define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */
70 #define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */
72 #define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */
73 #define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */
75 #define ADC_VREF_CAP 100 /* VREF capacitor in uF */
76 #define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
77 #define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
78 #define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
79 /* Wait at least 4100 LRCLK's */
81 #define ADC_REG1_FRAME_START 0x80 /* Frame start */
82 #define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
83 #define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */
84 #define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */
86 #define ADC_REG2_128x 0x80 /* Oversample at 128x */
87 #define ADC_REG2_CAL 0x40 /* System calibration enable */
88 #define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */
89 #define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */
90 #define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */
91 #define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */
92 #define ADC_REG2_DFS 0x02 /* Digital format select */
93 #define ADC_REG2_MUTE 0x01 /* Mute */
95 #define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */
96 #define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */
97 #define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */
98 #define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */
99 #define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */
100 #define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */
101 #define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */
107 #define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */
109 #define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */
110 #define DAC_RESET_DELAY 100 /* DAC reset delay in usec */
111 #define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */
113 #define DAC_REG1_AMUTE 0x80 /* Auto-mute */
115 #define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */
116 #define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */
117 #define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
118 #define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
119 #define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
120 #define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
122 #define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */
123 #define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */
124 #define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */
125 #define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */
127 #define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */
128 #define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */
129 #define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */
130 #define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */
132 #define DAC_REG5_INVERT_A 0x80 /* Invert channel A */
133 #define DAC_REG5_INVERT_B 0x40 /* Invert channel B */
134 #define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */
135 #define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */
136 #define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */
137 #define DAC_REG5_FREEZE 0x04 /* Freeze */
138 #define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
139 #define DAC_REG5_RESERVED 0x01 /* Reserved */
141 /* ------------------------------------------------------------------------- */
144 * Check Board Identity:
154 /* ------------------------------------------------------------------------- */
156 long int initdram(int board_type)
158 volatile immap_t *immap = (immap_t *)CFG_IMMR;
159 volatile memctl8260_t *memctl = &immap->im_memctl;
160 volatile uchar c = 0;
161 volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
162 uint psdmr = CFG_PSDMR;
164 uint psrt = 14; /* for no SPD */
165 uint chipselects = 1; /* for no SPD */
166 uint sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
167 uint or = CFG_OR2_PRELIM; /* for no SPD */
168 #ifdef SDRAM_SPD_ADDR
185 #ifdef SDRAM_SPD_ADDR
186 /* Keep the compiler from complaining about potentially uninitialized vars */
187 data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
190 * Read the SDRAM SPD EEPROM via I2C.
192 i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
195 for(j = 1; j < 64; j++) { /* read only the checksummed bytes */
196 /* note: the I2C address autoincrements when alen == 0 */
197 i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
198 if(j == 5) chipselects = data & 0x0F;
199 else if(j == 6) data_width = data;
200 else if(j == 7) data_width |= data << 8;
201 else if(j == 3) rows = data & 0x0F;
202 else if(j == 4) cols = data & 0x0F;
205 * Refresh rate: this assumes the prescaler is set to
206 * approximately 1uSec per tick.
208 switch(data & 0x7F) {
210 case 0: psrt = 14 ; /* 15.625uS */ break;
211 case 1: psrt = 2; /* 3.9uS */ break;
212 case 2: psrt = 6; /* 7.8uS */ break;
213 case 3: psrt = 29; /* 31.3uS */ break;
214 case 4: psrt = 60; /* 62.5uS */ break;
215 case 5: psrt = 120; /* 125uS */ break;
218 else if(j == 17) banks = data;
220 caslatency = 3; /* default CL */
221 #if(PESSIMISTIC_SDRAM)
222 if((data & 0x04) != 0) caslatency = 3;
223 else if((data & 0x02) != 0) caslatency = 2;
224 else if((data & 0x01) != 0) caslatency = 1;
226 if((data & 0x01) != 0) caslatency = 1;
227 else if((data & 0x02) != 0) caslatency = 2;
228 else if((data & 0x04) != 0) caslatency = 3;
231 printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
237 printf ("WARNING: Configuration data checksum failure:"
238 " is 0x%02x, calculated 0x%02x\n",
245 /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
247 printf("CL was %d, forcing to 2\n", caslatency);
251 printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
255 printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
259 if((data_width != 64) && (data_width != 72))
261 printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
264 width = 3; /* 2^3 = 8 bytes = 64 bits wide */
266 * Convert banks into log2(banks)
268 if (banks == 2) banks = 1;
269 else if(banks == 4) banks = 2;
270 else if(banks == 8) banks = 3;
272 sdram_size = 1 << (rows + cols + banks + width);
274 #if(CONFIG_PBI == 0) /* bank-based interleaving */
275 rowst = ((32 - 6) - (rows + cols + width)) * 2;
277 rowst = 32 - (rows + banks + cols + width);
280 or = ~(sdram_size - 1) | /* SDAM address mask */
281 ((banks-1) << 13) | /* banks per device */
282 (rowst << 9) | /* rowst */
283 ((rows - 9) << 6); /* numr */
285 memctl->memc_or2 = or;
288 * SDAM specifies the number of columns that are multiplexed
289 * (reference AN2165/D), defined to be (columns - 6) for page
290 * interleave, (columns - 8) for bank interleave.
292 * BSMA is 14 - max(rows, cols). The bank select lines come
293 * into play above the highest "address" line going into the
296 #if(CONFIG_PBI == 0) /* bank-based interleaving */
298 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
302 bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
305 #if(PESSIMISTIC_SDRAM)
306 psdmr = (CONFIG_PBI |\
315 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
320 psdmr = (CONFIG_PBI |\
323 PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
324 PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
325 PSDMR_WRC_1C | /* 1 clock + 7nSec */
329 ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
337 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
339 * "At system reset, initialization software must set up the
340 * programmable parameters in the memory controller banks registers
341 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
342 * system software should execute the following initialization sequence
343 * for each SDRAM device.
345 * 1. Issue a PRECHARGE-ALL-BANKS command
346 * 2. Issue eight CBR REFRESH commands
347 * 3. Issue a MODE-SET command to initialize the mode register
349 * Quote from Micron MT48LC8M16A2 data sheet:
351 * "...the SDRAM requires a 100uS delay prior to issuing any
352 * command other than a COMMAND INHIBIT or NOP. Starting at some
353 * point during this 100uS period and continuing at least through
354 * the end of this period, COMMAND INHIBIT or NOP commands should
357 * "Once the 100uS delay has been satisfied with at least one COMMAND
358 * INHIBIT or NOP command having been applied, a /PRECHARGE command/
359 * should be applied. All banks must then be precharged, thereby
360 * placing the device in the all banks idle state."
362 * "Once in the idle state, /two/ AUTO REFRESH cycles must be
363 * performed. After the AUTO REFRESH cycles are complete, the
364 * SDRAM is ready for mode register programming."
366 * (/emphasis/ mine, gvb)
368 * The way I interpret this, Micron start up sequence is:
369 * 1. Issue a PRECHARGE-BANK command (initial precharge)
370 * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
371 * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
372 * 4. Issue a MODE-SET command to initialize the mode register
376 * The initial commands are executed by setting P/LSDMR[OP] and
377 * accessing the SDRAM with a single-byte transaction."
379 * The appropriate BRx/ORx registers have already been set when we
380 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
383 memctl->memc_mptpr = CFG_MPTPR;
384 memctl->memc_psrt = psrt;
386 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
389 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
390 for (i = 0; i < 8; i++)
393 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
396 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
400 * Do it a second time for the second set of chips if the DIMM has
401 * two chip selects (double sided).
403 if(chipselects > 1) {
404 ramaddr += sdram_size;
406 memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
407 memctl->memc_or3 = or;
409 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
412 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
413 for (i = 0; i < 8; i++)
416 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
419 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
423 /* return total ram size */
424 return (sdram_size * chipselects);
427 /*-----------------------------------------------------------------------
428 * Board Control Functions
430 void board_poweroff (void)
432 while (1); /* hang forever */
436 #ifdef CONFIG_MISC_INIT_R
437 /* ------------------------------------------------------------------------- */
438 int misc_init_r(void)
441 * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
443 volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
444 volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
446 int reg; /* I2C register value */
447 char *ep; /* Environment pointer */
448 char str_buf[12] ; /* sprintf output buffer */
449 int sample_rate; /* ADC/DAC sample rate */
450 int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
451 int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
452 int right_just; /* Is the data to the DAC right justified? */
453 int mclk_divide; /* MCLK Divide */
456 * SACSng custom initialization:
457 * Start the ADC and DAC clocks, since the Crystal parts do not
458 * work on the I2C bus until the clocks are running.
461 sample_rate = INITIAL_SAMPLE_RATE;
462 if ((ep = getenv("DaqSampleRate")) != NULL) {
463 sample_rate = simple_strtol(ep, NULL, 10);
466 sample_64x = INITIAL_SAMPLE_64X;
467 sample_128x = INITIAL_SAMPLE_128X;
468 if ((ep = getenv("Daq64xSampling")) != NULL) {
469 sample_64x = simple_strtol(ep, NULL, 10);
478 if ((ep = getenv("Daq128xSampling")) != NULL) {
479 sample_128x = simple_strtol(ep, NULL, 10);
489 Daq_Init_Clocks(sample_rate, sample_64x);
490 sample_rate = Daq_Get_SampleRate();
491 Daq_Start_Clocks(sample_rate);
493 sprintf(str_buf, "%d", sample_rate);
494 setenv("DaqSampleRate", str_buf);
497 setenv("Daq64xSampling", "1");
498 setenv("Daq128xSampling", NULL);
501 setenv("Daq64xSampling", NULL);
502 setenv("Daq128xSampling", "1");
505 /* Display the ADC/DAC clocking information */
506 Daq_Display_Clocks();
509 * Determine the DAC data justification
512 right_just = INITIAL_RIGHT_JUST;
513 if ((ep = getenv("DaqDACRightJustified")) != NULL) {
514 right_just = simple_strtol(ep, NULL, 10);
517 sprintf(str_buf, "%d", right_just);
518 setenv("DaqDACRightJustified", str_buf);
521 * Determine the DAC MCLK Divide
524 mclk_divide = INITIAL_MCLK_DIVIDE;
525 if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
526 mclk_divide = simple_strtol(ep, NULL, 10);
529 sprintf(str_buf, "%d", mclk_divide);
530 setenv("DaqDACMClockDivide", str_buf);
533 * Initializing the I2C address in the Crystal A/Ds:
535 * 1) Wait for VREF cap to settle (10uSec per uF)
536 * 2) Release pullup on SDATA
537 * 3) Write the I2C address to register 6
538 * 4) Enable address matching by setting the MSB in register 7
541 printf("Initializing the ADC...\n");
542 udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
544 iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
545 udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
547 i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */
548 i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */
549 ADC_REG7_ADDR_ENABLE);
551 i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
552 (sample_64x ? 0 : ADC_REG2_128x) |
553 ADC_REG2_HIGH_PASS_DIS |
554 ADC_REG2_SLAVE_MODE);
556 reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
557 if(reg != I2C_ADC_1_ADDR)
558 printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
559 reg, I2C_ADC_1_ADDR);
561 iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
562 udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
564 i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */
566 i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
567 (sample_64x ? 0 : ADC_REG2_128x) |
568 ADC_REG2_HIGH_PASS_DIS |
569 ADC_REG2_SLAVE_MODE);
571 reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
572 if(reg != I2C_ADC_2_ADDR)
573 printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
574 reg, I2C_ADC_2_ADDR);
576 i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
577 ADC_REG1_FRAME_START |
578 ADC_REG1_GROUND_CAL);
580 i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
581 (sample_64x ? 0 : ADC_REG2_128x) |
583 ADC_REG2_HIGH_PASS_DIS |
584 ADC_REG2_SLAVE_MODE);
586 udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
587 i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
590 * Now that we have synchronized the ADC's, enable address
591 * selection on the second ADC as well as the first.
593 i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
596 * Initialize the Crystal DAC
598 * Two of the config lines are used for I2C so we have to set them
599 * to the proper initialization state without inadvertantly
600 * sending an I2C "start" sequence. When we bring the I2C back to
601 * the normal state, we send an I2C "stop" sequence.
603 printf("Initializing the DAC...\n");
606 * Bring the I2C clock and data lines low for initialization
615 iopa->pdat &= ~DAC_RST_MASK;
616 udelay(DAC_RESET_DELAY);
618 /* Release the DAC reset */
619 iopa->pdat |= DAC_RST_MASK;
620 udelay(DAC_INITIAL_DELAY);
624 * Enable control port (I2C mode)
625 * Going into power down
627 i2c_reg_write(I2C_DAC_ADDR, 0x05,
629 DAC_REG5_POWER_DOWN);
633 * Enable control port (I2C mode)
634 * Going into power down
638 i2c_reg_write(I2C_DAC_ADDR, 0x05,
640 DAC_REG5_POWER_DOWN |
641 (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
646 * . Format 0, left justified 24 bits
647 * . Format 3, right justified 24 bits
649 * . Single speed mode
650 * . Double speed mode
652 i2c_reg_write(I2C_DAC_ADDR, 0x01,
653 (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
654 DAC_REG1_LEFT_JUST_24_BIT) |
656 (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
658 sprintf(str_buf, "%d",
659 sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
660 setenv("DaqDACFunctionalMode", str_buf);
664 * Enable control port (I2C mode)
669 i2c_reg_write(I2C_DAC_ADDR, 0x05,
671 (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
674 * Create a I2C stop condition:
675 * low->high on data while clock is high.
685 #ifdef CONFIG_SHOW_BOOT_PROGRESS
687 * Turn off the RED fail LED now that we are up and running.
689 status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
695 #ifdef CONFIG_SHOW_BOOT_PROGRESS
697 * Show boot status: flash the LED if something goes wrong, indicating
698 * that last thing that worked and thus, by implication, what is broken.
700 * This stores the last OK value in RAM so this will not work properly
701 * before RAM is initialized. Since it is being used for indicating
702 * boot status (i.e. after RAM is initialized), that is OK.
704 static void flash_code(uchar number, uchar modulo, uchar digits)
709 * Recursively do upper digits.
712 flash_code(number / modulo, modulo, digits - 1);
715 number = number % modulo;
718 * Zero is indicated by one long flash (dash).
721 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
723 status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
727 * Non-zero is indicated by short flashes, one per count.
729 for(j = 0; j < number; j++) {
730 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
732 status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
737 * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
742 static int last_boot_progress;
744 void show_boot_progress (int status)
747 last_boot_progress = status;
750 * Houston, we have a problem. Blink the last OK status which
751 * indicates where things failed.
753 status_led_set(STATUS_LED_RED, STATUS_LED_ON);
754 flash_code(last_boot_progress, 5, 3);
756 status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
759 #endif /* CONFIG_SHOW_BOOT_PROGRESS */
763 * The following are used to control the SPI chip selects for the SPI command.
765 #if (CONFIG_COMMANDS & CFG_CMD_SPI)
767 #define SPI_ADC_CS_MASK 0x00000800
768 #define SPI_DAC_CS_MASK 0x00001000
770 void spi_adc_chipsel(int cs)
772 volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
775 iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */
777 iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */
780 void spi_dac_chipsel(int cs)
782 volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
785 iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */
787 iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */
791 * The SPI command uses this table of functions for controlling the SPI
792 * chip selects: it calls the appropriate function to control the SPI
795 spi_chipsel_type spi_chipsel[2] = {
799 #endif /* CFG_CMD_SPI */
801 #endif /* CONFIG_MISC_INIT_R */