2 * (C) Copyright 2013 SAMSUNG Electronics
3 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/board.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/dwmmc.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/power.h>
23 #include <power/pmic.h>
24 #include <asm/arch/sromc.h>
25 #include <power/max77686_pmic.h>
27 DECLARE_GLOBAL_DATA_PTR;
30 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
31 int cros_ec_err; /* Error for cros_ec, 0 if ok */
34 static struct local_info local;
36 #if defined CONFIG_EXYNOS_TMU
37 /* Boot Time Thermal Analysis for SoC temperature threshold breach */
38 static void boot_temp_check(void)
42 switch (tmu_monitor(&temp)) {
43 case TMU_STATUS_NORMAL:
45 case TMU_STATUS_TRIPPED:
47 * Status TRIPPED ans WARNING means corresponding threshold
50 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
54 case TMU_STATUS_WARNING:
55 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
59 * TMU_STATUS_INIT means something is wrong with temperature
60 * sensing and TMU status was changed back from NORMAL to INIT.
62 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
65 debug("EXYNOS_TMU: Unknown TMU state\n");
72 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
73 #if defined CONFIG_EXYNOS_TMU
74 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
75 debug("%s: Failed to init TMU\n", __func__);
81 #ifdef CONFIG_EXYNOS_SPI
92 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
93 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
94 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
99 void dram_init_banksize(void)
104 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
105 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
106 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
108 gd->bd->bi_dram[i].start = addr;
109 gd->bd->bi_dram[i].size = size;
113 static int board_uart_init(void)
115 int err, uart_id, ret = 0;
117 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
118 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
120 debug("UART%d not configured\n",
121 (uart_id - PERIPH_ID_UART0));
128 #ifdef CONFIG_BOARD_EARLY_INIT_F
129 int board_early_init_f(void)
133 err = board_uart_init();
135 debug("UART init failed\n");
139 #ifdef CONFIG_SYS_I2C_INIT_BOARD
140 board_i2c_init(gd->fdt_blob);
147 struct cros_ec_dev *board_get_cros_ec_dev(void)
149 return local.cros_ec_dev;
152 #ifdef CONFIG_CROS_EC
153 static int board_init_cros_ec_devices(const void *blob)
155 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
156 if (local.cros_ec_err)
157 return -1; /* Will report in board_late_init() */
163 #if defined(CONFIG_POWER)
164 #ifdef CONFIG_POWER_MAX77686
165 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
170 ret = pmic_reg_read(p, reg, &val);
172 debug("%s: PMIC %d register read failed\n", __func__, reg);
176 ret = pmic_reg_write(p, reg, val);
178 debug("%s: PMIC %d register write failed\n", __func__, reg);
184 static int max77686_init(void)
188 if (pmic_init(I2C_PMIC))
191 p = pmic_get("MAX77686_PMIC");
198 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
201 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
202 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
206 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
207 MAX77686_BUCK1OUT_1V)) {
208 debug("%s: PMIC %d register write failed\n", __func__,
209 MAX77686_REG_PMIC_BUCK1OUT);
213 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
214 MAX77686_BUCK1CTRL_EN))
218 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
219 MAX77686_BUCK2DVS1_1_3V)) {
220 debug("%s: PMIC %d register write failed\n", __func__,
221 MAX77686_REG_PMIC_BUCK2DVS1);
225 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
226 MAX77686_BUCK2CTRL_ON))
230 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
231 MAX77686_BUCK3DVS1_1_0125V)) {
232 debug("%s: PMIC %d register write failed\n", __func__,
233 MAX77686_REG_PMIC_BUCK3DVS1);
237 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
238 MAX77686_BUCK3CTRL_ON))
242 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
243 MAX77686_BUCK4DVS1_1_2V)) {
244 debug("%s: PMIC %d register write failed\n", __func__,
245 MAX77686_REG_PMIC_BUCK4DVS1);
249 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
250 MAX77686_BUCK3CTRL_ON))
254 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
255 MAX77686_LD02CTRL1_1_5V | EN_LDO))
259 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
260 MAX77686_LD03CTRL1_1_8V | EN_LDO))
264 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
265 MAX77686_LD05CTRL1_1_8V | EN_LDO))
269 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
270 MAX77686_LD10CTRL1_1_8V | EN_LDO))
277 int power_init_board(void)
283 #ifdef CONFIG_POWER_MAX77686
284 ret = max77686_init();
291 #ifdef CONFIG_OF_CONTROL
292 static int decode_sromc(const void *blob, struct fdt_sromc *config)
297 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
299 debug("Could not find SROMC node\n");
303 config->bank = fdtdec_get_int(blob, node, "bank", 0);
304 config->width = fdtdec_get_int(blob, node, "width", 2);
306 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
307 FDT_SROM_TIMING_COUNT);
309 debug("Could not decode SROMC configuration Error: %s\n",
311 return -FDT_ERR_NOTFOUND;
316 int board_eth_init(bd_t *bis)
318 #ifdef CONFIG_SMC911X
319 u32 smc_bw_conf, smc_bc_conf;
320 struct fdt_sromc config;
321 fdt_addr_t base_addr;
324 node = decode_sromc(gd->fdt_blob, &config);
326 debug("%s: Could not find sromc configuration\n", __func__);
329 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
331 debug("%s: Could not find lan9215 configuration\n", __func__);
335 /* We now have a node, so any problems from now on are errors */
336 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
337 if (base_addr == FDT_ADDR_T_NONE) {
338 debug("%s: Could not find lan9215 address\n", __func__);
342 /* Ethernet needs data bus width of 16 bits */
343 if (config.width != 2) {
344 debug("%s: Unsupported bus width %d\n", __func__,
348 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
349 | SROMC_BYTE_ENABLE(config.bank);
351 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
352 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
353 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
354 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
355 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
356 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
357 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
359 /* Select and configure the SROMC bank */
360 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
361 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
362 return smc911x_initialize(0, base_addr);
367 #ifdef CONFIG_GENERIC_MMC
368 int board_mmc_init(bd_t *bis)
372 /* dwmmc initializattion for available channels */
373 ret = exynos_dwmmc_init(gd->fdt_blob);
375 debug("dwmmc init failed\n");
382 #ifdef CONFIG_BOARD_LATE_INIT
383 int board_late_init(void)
385 stdio_print_current_devices();
387 if (local.cros_ec_err) {
388 /* Force console on */
389 gd->flags &= ~GD_FLG_SILENT;
391 printf("cros-ec communications failure %d\n",
393 puts("\nPlease reset with Power+Refresh\n\n");
394 panic("Cannot init cros-ec device");
401 int arch_early_init_r(void)
403 #ifdef CONFIG_CROS_EC
404 if (board_init_cros_ec_devices(gd->fdt_blob)) {
405 printf("%s: Failed to init EC\n", __func__);