2 * (C) Copyright 2013 SAMSUNG Electronics
3 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/board.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/dwmmc.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/power.h>
23 #include <power/pmic.h>
24 #include <asm/arch/sromc.h>
25 #include <power/max77686_pmic.h>
27 DECLARE_GLOBAL_DATA_PTR;
30 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
31 int cros_ec_err; /* Error for cros_ec, 0 if ok */
34 static struct local_info local;
36 #if defined CONFIG_EXYNOS_TMU
37 /* Boot Time Thermal Analysis for SoC temperature threshold breach */
38 static void boot_temp_check(void)
42 switch (tmu_monitor(&temp)) {
43 case TMU_STATUS_NORMAL:
45 case TMU_STATUS_TRIPPED:
47 * Status TRIPPED ans WARNING means corresponding threshold
50 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
54 case TMU_STATUS_WARNING:
55 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
59 * TMU_STATUS_INIT means something is wrong with temperature
60 * sensing and TMU status was changed back from NORMAL to INIT.
62 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
65 debug("EXYNOS_TMU: Unknown TMU state\n");
72 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
73 #if defined CONFIG_EXYNOS_TMU
74 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
75 debug("%s: Failed to init TMU\n", __func__);
81 #ifdef CONFIG_EXYNOS_SPI
92 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
93 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
94 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
99 void dram_init_banksize(void)
104 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
105 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
106 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
108 gd->bd->bi_dram[i].start = addr;
109 gd->bd->bi_dram[i].size = size;
113 static int board_uart_init(void)
115 int err, uart_id, ret = 0;
117 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
118 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
120 debug("UART%d not configured\n",
121 (uart_id - PERIPH_ID_UART0));
128 #ifdef CONFIG_BOARD_EARLY_INIT_F
129 int board_early_init_f(void)
133 err = board_uart_init();
135 debug("UART init failed\n");
139 #ifdef CONFIG_SYS_I2C_INIT_BOARD
140 board_i2c_init(gd->fdt_blob);
147 struct cros_ec_dev *board_get_cros_ec_dev(void)
149 return local.cros_ec_dev;
152 static int board_init_cros_ec_devices(const void *blob)
154 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
155 if (local.cros_ec_err)
156 return -1; /* Will report in board_late_init() */
161 #if defined(CONFIG_POWER)
162 #ifdef CONFIG_POWER_MAX77686
163 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
168 ret = pmic_reg_read(p, reg, &val);
170 debug("%s: PMIC %d register read failed\n", __func__, reg);
174 ret = pmic_reg_write(p, reg, val);
176 debug("%s: PMIC %d register write failed\n", __func__, reg);
182 static int max77686_init(void)
186 if (pmic_init(I2C_PMIC))
189 p = pmic_get("MAX77686_PMIC");
196 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
199 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
200 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
204 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
205 MAX77686_BUCK1OUT_1V)) {
206 debug("%s: PMIC %d register write failed\n", __func__,
207 MAX77686_REG_PMIC_BUCK1OUT);
211 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
212 MAX77686_BUCK1CTRL_EN))
216 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
217 MAX77686_BUCK2DVS1_1_3V)) {
218 debug("%s: PMIC %d register write failed\n", __func__,
219 MAX77686_REG_PMIC_BUCK2DVS1);
223 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
224 MAX77686_BUCK2CTRL_ON))
228 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
229 MAX77686_BUCK3DVS1_1_0125V)) {
230 debug("%s: PMIC %d register write failed\n", __func__,
231 MAX77686_REG_PMIC_BUCK3DVS1);
235 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
236 MAX77686_BUCK3CTRL_ON))
240 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
241 MAX77686_BUCK4DVS1_1_2V)) {
242 debug("%s: PMIC %d register write failed\n", __func__,
243 MAX77686_REG_PMIC_BUCK4DVS1);
247 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
248 MAX77686_BUCK3CTRL_ON))
252 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
253 MAX77686_LD02CTRL1_1_5V | EN_LDO))
257 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
258 MAX77686_LD03CTRL1_1_8V | EN_LDO))
262 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
263 MAX77686_LD05CTRL1_1_8V | EN_LDO))
267 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
268 MAX77686_LD10CTRL1_1_8V | EN_LDO))
275 int power_init_board(void)
281 #ifdef CONFIG_POWER_MAX77686
282 ret = max77686_init();
289 #ifdef CONFIG_OF_CONTROL
290 static int decode_sromc(const void *blob, struct fdt_sromc *config)
295 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
297 debug("Could not find SROMC node\n");
301 config->bank = fdtdec_get_int(blob, node, "bank", 0);
302 config->width = fdtdec_get_int(blob, node, "width", 2);
304 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
305 FDT_SROM_TIMING_COUNT);
307 debug("Could not decode SROMC configuration Error: %s\n",
309 return -FDT_ERR_NOTFOUND;
314 int board_eth_init(bd_t *bis)
316 #ifdef CONFIG_SMC911X
317 u32 smc_bw_conf, smc_bc_conf;
318 struct fdt_sromc config;
319 fdt_addr_t base_addr;
322 node = decode_sromc(gd->fdt_blob, &config);
324 debug("%s: Could not find sromc configuration\n", __func__);
327 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
329 debug("%s: Could not find lan9215 configuration\n", __func__);
333 /* We now have a node, so any problems from now on are errors */
334 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
335 if (base_addr == FDT_ADDR_T_NONE) {
336 debug("%s: Could not find lan9215 address\n", __func__);
340 /* Ethernet needs data bus width of 16 bits */
341 if (config.width != 2) {
342 debug("%s: Unsupported bus width %d\n", __func__,
346 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
347 | SROMC_BYTE_ENABLE(config.bank);
349 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
350 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
351 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
352 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
353 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
354 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
355 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
357 /* Select and configure the SROMC bank */
358 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
359 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
360 return smc911x_initialize(0, base_addr);
365 #ifdef CONFIG_GENERIC_MMC
366 int board_mmc_init(bd_t *bis)
370 /* dwmmc initializattion for available channels */
371 ret = exynos_dwmmc_init(gd->fdt_blob);
373 debug("dwmmc init failed\n");
380 #ifdef CONFIG_BOARD_LATE_INIT
381 int board_late_init(void)
383 stdio_print_current_devices();
385 if (local.cros_ec_err) {
386 /* Force console on */
387 gd->flags &= ~GD_FLG_SILENT;
389 printf("cros-ec communications failure %d\n",
391 puts("\nPlease reset with Power+Refresh\n\n");
392 panic("Cannot init cros-ec device");
399 int arch_early_init_r(void)
401 #ifdef CONFIG_CROS_EC
402 if (board_init_cros_ec_devices(gd->fdt_blob)) {
403 printf("%s: Failed to init EC\n", __func__);