2 * (C) Copyright 2013 SAMSUNG Electronics
3 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/board.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/dwmmc.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/power.h>
23 #include <power/pmic.h>
24 #include <asm/arch/sromc.h>
25 #include <power/max77686_pmic.h>
27 DECLARE_GLOBAL_DATA_PTR;
30 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
31 int cros_ec_err; /* Error for cros_ec, 0 if ok */
34 static struct local_info local;
36 int __exynos_early_init_f(void)
40 int exynos_early_init_f(void)
41 __attribute__((weak, alias("__exynos_early_init_f")));
43 int __exynos_power_init(void)
47 int exynos_power_init(void)
48 __attribute__((weak, alias("__exynos_power_init")));
50 #if defined CONFIG_EXYNOS_TMU
51 /* Boot Time Thermal Analysis for SoC temperature threshold breach */
52 static void boot_temp_check(void)
56 switch (tmu_monitor(&temp)) {
57 case TMU_STATUS_NORMAL:
59 case TMU_STATUS_TRIPPED:
61 * Status TRIPPED ans WARNING means corresponding threshold
64 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
68 case TMU_STATUS_WARNING:
69 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
73 * TMU_STATUS_INIT means something is wrong with temperature
74 * sensing and TMU status was changed back from NORMAL to INIT.
76 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
79 debug("EXYNOS_TMU: Unknown TMU state\n");
86 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
87 #if defined CONFIG_EXYNOS_TMU
88 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
89 debug("%s: Failed to init TMU\n", __func__);
95 #ifdef CONFIG_EXYNOS_SPI
106 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
107 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
108 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
113 void dram_init_banksize(void)
118 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
119 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
120 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
122 gd->bd->bi_dram[i].start = addr;
123 gd->bd->bi_dram[i].size = size;
127 static int board_uart_init(void)
129 int err, uart_id, ret = 0;
131 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
132 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
134 debug("UART%d not configured\n",
135 (uart_id - PERIPH_ID_UART0));
142 #ifdef CONFIG_BOARD_EARLY_INIT_F
143 int board_early_init_f(void)
147 err = board_uart_init();
149 debug("UART init failed\n");
153 #ifdef CONFIG_SYS_I2C_INIT_BOARD
154 board_i2c_init(gd->fdt_blob);
157 return exynos_early_init_f();
161 struct cros_ec_dev *board_get_cros_ec_dev(void)
163 return local.cros_ec_dev;
166 #ifdef CONFIG_CROS_EC
167 static int board_init_cros_ec_devices(const void *blob)
169 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
170 if (local.cros_ec_err)
171 return -1; /* Will report in board_late_init() */
177 #if defined(CONFIG_POWER)
178 #ifdef CONFIG_POWER_MAX77686
179 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
184 ret = pmic_reg_read(p, reg, &val);
186 debug("%s: PMIC %d register read failed\n", __func__, reg);
190 ret = pmic_reg_write(p, reg, val);
192 debug("%s: PMIC %d register write failed\n", __func__, reg);
198 static int max77686_init(void)
202 if (pmic_init(I2C_PMIC))
205 p = pmic_get("MAX77686_PMIC");
212 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
215 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
216 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
220 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
221 MAX77686_BUCK1OUT_1V)) {
222 debug("%s: PMIC %d register write failed\n", __func__,
223 MAX77686_REG_PMIC_BUCK1OUT);
227 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
228 MAX77686_BUCK1CTRL_EN))
232 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
233 MAX77686_BUCK2DVS1_1_3V)) {
234 debug("%s: PMIC %d register write failed\n", __func__,
235 MAX77686_REG_PMIC_BUCK2DVS1);
239 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
240 MAX77686_BUCK2CTRL_ON))
244 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
245 MAX77686_BUCK3DVS1_1_0125V)) {
246 debug("%s: PMIC %d register write failed\n", __func__,
247 MAX77686_REG_PMIC_BUCK3DVS1);
251 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
252 MAX77686_BUCK3CTRL_ON))
256 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
257 MAX77686_BUCK4DVS1_1_2V)) {
258 debug("%s: PMIC %d register write failed\n", __func__,
259 MAX77686_REG_PMIC_BUCK4DVS1);
263 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
264 MAX77686_BUCK3CTRL_ON))
268 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
269 MAX77686_LD02CTRL1_1_5V | EN_LDO))
273 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
274 MAX77686_LD03CTRL1_1_8V | EN_LDO))
278 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
279 MAX77686_LD05CTRL1_1_8V | EN_LDO))
283 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
284 MAX77686_LD10CTRL1_1_8V | EN_LDO))
291 int power_init_board(void)
297 #ifdef CONFIG_POWER_MAX77686
298 ret = max77686_init();
301 return exynos_power_init();
305 #ifdef CONFIG_OF_CONTROL
306 static int decode_sromc(const void *blob, struct fdt_sromc *config)
311 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
313 debug("Could not find SROMC node\n");
317 config->bank = fdtdec_get_int(blob, node, "bank", 0);
318 config->width = fdtdec_get_int(blob, node, "width", 2);
320 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
321 FDT_SROM_TIMING_COUNT);
323 debug("Could not decode SROMC configuration Error: %s\n",
325 return -FDT_ERR_NOTFOUND;
330 int board_eth_init(bd_t *bis)
332 #ifdef CONFIG_SMC911X
333 u32 smc_bw_conf, smc_bc_conf;
334 struct fdt_sromc config;
335 fdt_addr_t base_addr;
338 node = decode_sromc(gd->fdt_blob, &config);
340 debug("%s: Could not find sromc configuration\n", __func__);
343 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
345 debug("%s: Could not find lan9215 configuration\n", __func__);
349 /* We now have a node, so any problems from now on are errors */
350 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
351 if (base_addr == FDT_ADDR_T_NONE) {
352 debug("%s: Could not find lan9215 address\n", __func__);
356 /* Ethernet needs data bus width of 16 bits */
357 if (config.width != 2) {
358 debug("%s: Unsupported bus width %d\n", __func__,
362 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
363 | SROMC_BYTE_ENABLE(config.bank);
365 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
366 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
367 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
368 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
369 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
370 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
371 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
373 /* Select and configure the SROMC bank */
374 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
375 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
376 return smc911x_initialize(0, base_addr);
381 #ifdef CONFIG_GENERIC_MMC
382 int board_mmc_init(bd_t *bis)
386 /* dwmmc initializattion for available channels */
387 ret = exynos_dwmmc_init(gd->fdt_blob);
389 debug("dwmmc init failed\n");
395 #ifdef CONFIG_DISPLAY_BOARDINFO
398 const char *board_name;
400 board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
401 printf("Board: %s\n", board_name ? board_name : "unknown");
406 #endif /* CONFIG_OF_CONTROL */
408 #ifdef CONFIG_BOARD_LATE_INIT
409 int board_late_init(void)
411 stdio_print_current_devices();
413 if (local.cros_ec_err) {
414 /* Force console on */
415 gd->flags &= ~GD_FLG_SILENT;
417 printf("cros-ec communications failure %d\n",
419 puts("\nPlease reset with Power+Refresh\n\n");
420 panic("Cannot init cros-ec device");
427 int arch_early_init_r(void)
429 #ifdef CONFIG_CROS_EC
430 if (board_init_cros_ec_devices(gd->fdt_blob)) {
431 printf("%s: Failed to init EC\n", __func__);