2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/power.h>
36 * r7 has S5PC100 GPIO base, 0xE0300000
37 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
38 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
48 /* r5 has always zero */
51 ldr r7, =S5PC100_GPIO_BASE
52 ldr r8, =S5PC100_GPIO_BASE
54 ldr r2, =S5PC1XX_PRO_ID
60 ldr r8, =S5PC110_GPIO_BASE
62 /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
64 beq skip_check_didle @ Support C110 only
66 ldr r0, =S5PC110_RST_STAT
68 and r1, r1, #0x000D0000
69 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
74 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
75 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
76 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
77 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
78 orr r1, r1, #(0x1 << 4)
79 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
81 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
82 #ifdef CONFIG_ONENAND_IPL
83 orr r1, r1, #(1 << 1) @ 1 * 1-bit
87 str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
89 /* Don't setup at s5pc100 */
93 * Initialize Async Register Setting for EVT1
94 * Because we are setting EVT1 as the default value of EVT0,
95 * setting EVT0 as well does not make things worse.
96 * Thus, for the simplicity, we set for EVT0, too
98 * The "Async Registers" are:
167 * Diable ABB block to reduce sleep current at low temperature
168 * Note that it's hidden register setup don't modify it
175 /* IO retension release */
176 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
177 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
179 ldreq r2, =(1 << 31) @ IO_RET_REL
180 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
182 /* Do not release retention here for S5PC110 */
185 #ifndef CONFIG_ONENAND_IPL
186 /* Disable Watchdog */
187 ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
188 ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
192 ldreq r0, =S5PC100_SROMC_BASE
193 ldrne r0, =S5PC110_SROMC_BASE
198 /* S5PC100 has 3 groups of interrupt sources */
199 ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
200 ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
201 add r1, r0, #0x00100000
202 add r2, r0, #0x00200000
204 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
206 str r3, [r0, #0x14] @ INTENCLEAR
207 str r3, [r1, #0x14] @ INTENCLEAR
208 str r3, [r2, #0x14] @ INTENCLEAR
210 #ifndef CONFIG_ONENAND_IPL
211 /* Set all interrupts as IRQ */
212 str r5, [r0, #0xc] @ INTSELECT
213 str r5, [r1, #0xc] @ INTSELECT
214 str r5, [r2, #0xc] @ INTSELECT
216 /* Pending Interrupt Clear */
217 str r5, [r0, #0xf00] @ INTADDRESS
218 str r5, [r1, #0xf00] @ INTADDRESS
219 str r5, [r2, #0xf00] @ INTADDRESS
222 #ifndef CONFIG_ONENAND_IPL
229 #ifdef CONFIG_ONENAND_IPL
230 /* init system clock */
233 /* OneNAND Sync Read Support at S5PC110 only
235 * BRWL[14:12] : 7 CLK
236 * BL[11:9] : Continuous
237 * VHF[3] : Very High Frequency Enable (Over 83MHz)
238 * HF[2] : High Frequency Enable (Over 66MHz)
243 ldrne r0, =0xB001E442
247 * GCE[26] : Gated Clock Enable
248 * RPE[17] : Enables Read Prefetch
250 ldrne r1, =((1 << 26) | (1 << 17) | 0xE006)
251 ldrne r0, =0xB0600000
252 strne r1, [r0, #0x100] @ ONENAND_IF_CTRL
254 strne r1, [r0, #0x108]
256 /* Board detection to set proper memory configuration */
258 moveq r9, #1 /* r9 has 1Gib default at s5pc100 */
259 movne r9, #2 /* r9 has 2Gib default at s5pc110 */
264 bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */
265 bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */
266 bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */
268 /* For write completion */
273 and r1, r3, #(0x7 << 2)
281 and r0, r3, #(0x1 << 1)
283 orr r1, r1, r0, lsl #3
286 and r1, r3, #(0x7 << 2)
288 and r0, r3, #(0x1 << 7)
290 orr r1, r1, r0, lsl #3
293 str r4, [r2, #0x48] /* Restore PULLUP configuration */
297 /* Wakeup support. Don't know if it's going to be used, untested. */
298 ldreq r0, =S5PC100_RST_STAT
299 ldrne r0, =S5PC110_RST_STAT
301 biceq r1, r1, #0xfffffff7
303 bicne r1, r1, #0xfffeffff
308 /* turn off L2 cache */
315 /* invalidate L2 cache also */
318 /* turn on L2 cache */
322 /* Load return address and jump to kernel */
323 ldreq r0, =S5PC100_INFORM0
324 ldrne r0, =S5PC110_INFORM0
326 /* r1 = physical address of s5pc1xx_cpu_resume function */
329 /* Jump to kernel (sleep-s5pc1xx.S) */
335 /* Clear wakeup status register */
336 ldreq r0, =S5PC100_WAKEUP_STAT
337 ldrne r0, =S5PC110_WAKEUP_STAT
341 /* IO retension release */
342 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
343 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
345 ldreq r2, =(1 << 31) @ IO_RET_REL
346 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
354 /* Wait when APLL is locked */
355 ldr r0, =0xE0100100 @ S5PC110_APLL_CON
358 and r1, r1, #(1 << 29)
362 ldr r0, =S5PC110_INFORM0
376 * system_clock_init: Initialize core clock and bus clock.
377 * void system_clock_init(void)
380 ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
387 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
388 str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
389 str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
390 str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
391 str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
394 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
397 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
400 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
403 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
420 /* Set Source Clock */
421 ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
422 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
426 ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
428 /* Set OSC_FREQ value */
430 str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
432 /* Set MTC_STABLE value */
434 str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
436 /* Set CLAMP_STABLE value */
438 str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
440 ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000
442 /* Set Clock divider */
443 ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
445 ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
449 ldr r1, =0x2cf @ Locktime : 30us
450 str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
451 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
452 str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
453 str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
454 str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
456 /* S5PC110_APLL_CON */
457 ldr r1, =0x80C80601 @ 800MHz
459 /* S5PC110_MPLL_CON */
460 ldr r1, =0x829B0C01 @ 667MHz
462 /* S5PC110_EPLL_CON */
463 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
465 /* S5PC110_VPLL_CON */
466 ldr r1, =0x806C0603 @ 54MHz
469 /* Set Source Clock */
470 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
471 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
473 /* OneDRAM(DMC0) clock setting */
474 ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
475 str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
476 ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
477 str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
479 /* XCLKOUT = XUSBXTI 24MHz */
480 add r2, r0, #0xE000 @ S5PC110_OTHERS
482 orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
486 ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
487 str r1, [r0, #0x460] @ S5PC110_CLK_IP0
490 ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
492 str r1, [r0, #0x464] @ S5PC110_CLK_IP1
495 ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
496 @ HOSTIF[10] HSMMC0[16]
497 @ HSMMC2[18] VIC[27:24]
498 str r1, [r0, #0x468] @ S5PC110_CLK_IP2
501 ldr r1, =0x8eff038c @ I2C[8:6]
502 @ SYSTIMER[16] UART0[17]
503 @ UART1[18] UART2[19]
505 @ PWM[23] GPIO[26] SYSCON[27]
506 str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
509 ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
510 str r1, [r0, #0x470] @ S5PC110_CLK_IP3
513 /* wait at least 200us to stablize all clock */
520 #ifndef CONFIG_ONENAND_IPL
522 ldreq r0, =0xE3800000
523 ldrne r0, =0xF1500000
530 #ifndef CONFIG_ONENAND_IPL
532 * uart_asm_init: Initialize UART's pins
535 /* set GPIO to enable UART0-UART4 */
538 str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
540 str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
546 /* UART_SEL GPK0[5] at S5PC100 */
547 add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
548 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
549 bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
550 orr r1, r1, #(0x1 << 20) @ Output
551 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
553 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
554 bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
555 orr r1, r1, #(0x2 << 10) @ Pull-up enabled
556 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
558 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
559 orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
560 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
565 * Note that the following address
566 * 0xE020'0360 is reserved address at S5PC100
568 /* UART_SEL MP0_5[7] at S5PC110 */
569 add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
570 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
571 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
572 orr r1, r1, #(0x1 << 28) @ Output
573 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
575 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
576 bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
577 orr r1, r1, #(0x2 << 14) @ Pull-up enabled
578 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
580 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
581 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
582 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET