2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/power.h>
20 * r7 has S5PC100 GPIO base, 0xE0300000
21 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
22 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
29 /* r5 has always zero */
32 ldr r7, =S5PC100_GPIO_BASE
33 ldr r8, =S5PC100_GPIO_BASE
35 ldr r2, =S5PC110_PRO_ID
41 ldr r8, =S5PC110_GPIO_BASE
43 /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
45 beq skip_check_didle @ Support C110 only
47 ldr r0, =S5PC110_RST_STAT
49 and r1, r1, #0x000D0000
50 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
55 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
56 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
57 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
58 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
59 orr r1, r1, #(0x1 << 4)
60 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
62 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
64 str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
66 /* Don't setup at s5pc100 */
70 * Initialize Async Register Setting for EVT1
71 * Because we are setting EVT1 as the default value of EVT0,
72 * setting EVT0 as well does not make things worse.
73 * Thus, for the simplicity, we set for EVT0, too
75 * The "Async Registers" are:
144 * Diable ABB block to reduce sleep current at low temperature
145 * Note that it's hidden register setup don't modify it
152 /* IO retension release */
153 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
154 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
156 ldreq r2, =(1 << 31) @ IO_RET_REL
157 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
159 /* Do not release retention here for S5PC110 */
162 /* Disable Watchdog */
163 ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
164 ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
168 ldreq r0, =S5PC100_SROMC_BASE
169 ldrne r0, =S5PC110_SROMC_BASE
173 /* S5PC100 has 3 groups of interrupt sources */
174 ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
175 ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
176 add r1, r0, #0x00100000
177 add r2, r0, #0x00200000
179 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
181 str r3, [r0, #0x14] @ INTENCLEAR
182 str r3, [r1, #0x14] @ INTENCLEAR
183 str r3, [r2, #0x14] @ INTENCLEAR
185 /* Set all interrupts as IRQ */
186 str r5, [r0, #0xc] @ INTSELECT
187 str r5, [r1, #0xc] @ INTSELECT
188 str r5, [r2, #0xc] @ INTSELECT
190 /* Pending Interrupt Clear */
191 str r5, [r0, #0xf00] @ INTADDRESS
192 str r5, [r1, #0xf00] @ INTADDRESS
193 str r5, [r2, #0xf00] @ INTADDRESS
201 /* Clear wakeup status register */
202 ldreq r0, =S5PC100_WAKEUP_STAT
203 ldrne r0, =S5PC110_WAKEUP_STAT
207 /* IO retension release */
208 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
209 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
211 ldreq r2, =(1 << 31) @ IO_RET_REL
212 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
219 /* Wait when APLL is locked */
220 ldr r0, =0xE0100100 @ S5PC110_APLL_CON
223 and r1, r1, #(1 << 29)
227 ldr r0, =S5PC110_INFORM0
241 * system_clock_init: Initialize core clock and bus clock.
242 * void system_clock_init(void)
245 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
252 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
253 str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
254 str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
255 str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
256 str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
259 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
262 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
265 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
268 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
285 /* Set Source Clock */
286 ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
287 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
291 ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
293 /* Set OSC_FREQ value */
295 str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
297 /* Set MTC_STABLE value */
299 str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
301 /* Set CLAMP_STABLE value */
303 str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
305 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
307 /* Set Clock divider */
308 ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
310 ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
314 ldr r1, =0x2cf @ Locktime : 30us
315 str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
316 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
317 str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
318 str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
319 str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
321 /* S5PC110_APLL_CON */
322 ldr r1, =0x80C80601 @ 800MHz
324 /* S5PC110_MPLL_CON */
325 ldr r1, =0x829B0C01 @ 667MHz
327 /* S5PC110_EPLL_CON */
328 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
330 /* S5PC110_VPLL_CON */
331 ldr r1, =0x806C0603 @ 54MHz
334 /* Set Source Clock */
335 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
336 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
338 /* OneDRAM(DMC0) clock setting */
339 ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
340 str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
341 ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
342 str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
344 /* XCLKOUT = XUSBXTI 24MHz */
345 add r2, r0, #0xE000 @ S5PC110_OTHERS
347 orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
351 ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
352 str r1, [r0, #0x460] @ S5PC110_CLK_IP0
355 ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
357 str r1, [r0, #0x464] @ S5PC110_CLK_IP1
360 ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
361 @ HOSTIF[10] HSMMC0[16]
362 @ HSMMC2[18] VIC[27:24]
363 str r1, [r0, #0x468] @ S5PC110_CLK_IP2
366 ldr r1, =0x8eff038c @ I2C[8:6]
367 @ SYSTIMER[16] UART0[17]
368 @ UART1[18] UART2[19]
370 @ PWM[23] GPIO[26] SYSCON[27]
371 str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
374 ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
375 str r1, [r0, #0x470] @ S5PC110_CLK_IP3
378 /* wait at least 200us to stablize all clock */
386 ldreq r0, =0xE3800000
387 ldrne r0, =0xF1500000
394 * uart_asm_init: Initialize UART's pins
397 /* set GPIO to enable UART0-UART4 */
400 str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
402 str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
408 /* UART_SEL GPK0[5] at S5PC100 */
409 add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
410 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
411 bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
412 orr r1, r1, #(0x1 << 20) @ Output
413 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
415 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
416 bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
417 orr r1, r1, #(0x2 << 10) @ Pull-up enabled
418 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
420 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
421 orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
422 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
427 * Note that the following address
428 * 0xE020'0360 is reserved address at S5PC100
430 /* UART_SEL MP0_5[7] at S5PC110 */
431 add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
432 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
433 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
434 orr r1, r1, #(0x1 << 28) @ Output
435 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
437 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
438 bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
439 orr r1, r1, #(0x2 << 14) @ Pull-up enabled
440 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
442 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
443 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
444 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET