2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/power.h>
19 * r7 has S5PC100 GPIO base, 0xE0300000
20 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
21 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
28 /* r5 has always zero */
31 ldr r7, =S5PC100_GPIO_BASE
32 ldr r8, =S5PC100_GPIO_BASE
34 ldr r2, =S5PC110_PRO_ID
40 ldr r8, =S5PC110_GPIO_BASE
42 /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
44 beq skip_check_didle @ Support C110 only
46 ldr r0, =S5PC110_RST_STAT
48 and r1, r1, #0x000D0000
49 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
54 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
55 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
56 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
57 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
58 orr r1, r1, #(0x1 << 4)
59 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
61 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
63 str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
65 /* Don't setup at s5pc100 */
69 * Initialize Async Register Setting for EVT1
70 * Because we are setting EVT1 as the default value of EVT0,
71 * setting EVT0 as well does not make things worse.
72 * Thus, for the simplicity, we set for EVT0, too
74 * The "Async Registers" are:
143 * Diable ABB block to reduce sleep current at low temperature
144 * Note that it's hidden register setup don't modify it
151 /* IO retension release */
152 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
153 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
155 ldreq r2, =(1 << 31) @ IO_RET_REL
156 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
158 /* Do not release retention here for S5PC110 */
161 /* Disable Watchdog */
162 ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
163 ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
167 ldreq r0, =S5PC100_SROMC_BASE
168 ldrne r0, =S5PC110_SROMC_BASE
172 /* S5PC100 has 3 groups of interrupt sources */
173 ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
174 ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
175 add r1, r0, #0x00100000
176 add r2, r0, #0x00200000
178 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
180 str r3, [r0, #0x14] @ INTENCLEAR
181 str r3, [r1, #0x14] @ INTENCLEAR
182 str r3, [r2, #0x14] @ INTENCLEAR
184 /* Set all interrupts as IRQ */
185 str r5, [r0, #0xc] @ INTSELECT
186 str r5, [r1, #0xc] @ INTSELECT
187 str r5, [r2, #0xc] @ INTSELECT
189 /* Pending Interrupt Clear */
190 str r5, [r0, #0xf00] @ INTADDRESS
191 str r5, [r1, #0xf00] @ INTADDRESS
192 str r5, [r2, #0xf00] @ INTADDRESS
200 /* Clear wakeup status register */
201 ldreq r0, =S5PC100_WAKEUP_STAT
202 ldrne r0, =S5PC110_WAKEUP_STAT
206 /* IO retension release */
207 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
208 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
210 ldreq r2, =(1 << 31) @ IO_RET_REL
211 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
218 /* Wait when APLL is locked */
219 ldr r0, =0xE0100100 @ S5PC110_APLL_CON
222 and r1, r1, #(1 << 29)
226 ldr r0, =S5PC110_INFORM0
240 * system_clock_init: Initialize core clock and bus clock.
241 * void system_clock_init(void)
244 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
251 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
252 str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
253 str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
254 str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
255 str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
258 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
261 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
264 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
267 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
284 /* Set Source Clock */
285 ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
286 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
290 ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
292 /* Set OSC_FREQ value */
294 str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
296 /* Set MTC_STABLE value */
298 str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
300 /* Set CLAMP_STABLE value */
302 str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
304 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
306 /* Set Clock divider */
307 ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
309 ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
313 ldr r1, =0x2cf @ Locktime : 30us
314 str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
315 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
316 str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
317 str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
318 str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
320 /* S5PC110_APLL_CON */
321 ldr r1, =0x80C80601 @ 800MHz
323 /* S5PC110_MPLL_CON */
324 ldr r1, =0x829B0C01 @ 667MHz
326 /* S5PC110_EPLL_CON */
327 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
329 /* S5PC110_VPLL_CON */
330 ldr r1, =0x806C0603 @ 54MHz
333 /* Set Source Clock */
334 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
335 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
337 /* OneDRAM(DMC0) clock setting */
338 ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
339 str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
340 ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
341 str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
343 /* XCLKOUT = XUSBXTI 24MHz */
344 add r2, r0, #0xE000 @ S5PC110_OTHERS
346 orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
350 ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
351 str r1, [r0, #0x460] @ S5PC110_CLK_IP0
354 ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
356 str r1, [r0, #0x464] @ S5PC110_CLK_IP1
359 ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
360 @ HOSTIF[10] HSMMC0[16]
361 @ HSMMC2[18] VIC[27:24]
362 str r1, [r0, #0x468] @ S5PC110_CLK_IP2
365 ldr r1, =0x8eff038c @ I2C[8:6]
366 @ SYSTIMER[16] UART0[17]
367 @ UART1[18] UART2[19]
369 @ PWM[23] GPIO[26] SYSCON[27]
370 str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
373 ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
374 str r1, [r0, #0x470] @ S5PC110_CLK_IP3
377 /* wait at least 200us to stablize all clock */
385 ldreq r0, =0xE3800000
386 ldrne r0, =0xF1500000
393 * uart_asm_init: Initialize UART's pins
396 /* set GPIO to enable UART0-UART4 */
399 str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
401 str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
407 /* UART_SEL GPK0[5] at S5PC100 */
408 add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
409 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
410 bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
411 orr r1, r1, #(0x1 << 20) @ Output
412 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
414 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
415 bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
416 orr r1, r1, #(0x2 << 10) @ Pull-up enabled
417 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
419 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
420 orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
421 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
426 * Note that the following address
427 * 0xE020'0360 is reserved address at S5PC100
429 /* UART_SEL MP0_5[7] at S5PC110 */
430 add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
431 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
432 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
433 orr r1, r1, #(0x1 << 28) @ Output
434 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
436 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
437 bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
438 orr r1, r1, #(0x2 << 14) @ Pull-up enabled
439 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
441 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
442 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
443 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET