2 * Copyright (C) 2009 Samsung Electrnoics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 .globl mem_ctrl_asm_init
31 ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000
32 ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000
33 ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000
35 /* DLL parameter setting */
37 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
38 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
40 str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET
41 strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET
43 streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET
47 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
48 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
52 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
53 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
56 wait: subs r2, r2, #0x1
61 /* Force value locking for DLL off */
62 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
63 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
67 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
68 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
70 /* auto refresh off */
71 ldr r1, =0xff001010 | (1 << 7)
72 ldr r2, =0xff001010 | (1 << 7)
73 str r1, [r0, #0x000] @ CONCONTROL_OFFSET
74 strne r2, [r6, #0x000] @ CONCONTROL_OFFSET
77 * Burst Length 4, 2 chips, 32-bit, LPDDR
78 * OFF: dynamic self refresh, force precharge, dynamic power down off
82 str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
83 strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET
87 * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
88 * So finally Bank1 OneDRAM should address start at at 0x3000'0000
92 * DMC0: CS0 : S5PC100/S5PC110
103 str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET
104 str r4, [r0, #0x00C] @ dummy write
107 * DMC1: CS0 : S5PC110
109 * 0xf8 -> 0x47FFFFFF (1Gib)
111 * 0xf0 -> 0x4FFFFFFF (2Gib)
113 * [11:8 ] 2: 9 bits - Col (1Gib)
114 * [11:8 ] 3: 10 bits - Col (2Gib)
115 * [ 7:4 ] 2: 14 bits - Row
119 ldr r4, =0x40f01322 @ 2Gib: MCP B
120 ldr r5, =0x50f81312 @ dummy: MCP D
122 ldreq r4, =0x40f81222 @ 1Gib: MCP A
124 ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D
126 ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E
129 strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET
130 strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET
141 eoreq r3, r3, #0x08000000
142 streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET
145 str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
146 strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
147 strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET
157 * 7.8us * 200MHz %LE %LONG1560(0x618)
158 * 7.8us * 166MHz %LE %LONG1294(0x50E)
159 * 7.8us * 133MHz %LE %LONG1038(0x40E),
160 * 7.8us * 100MHz %LE %LONG780(0x30C),
163 str r1, [r0, #0x030] @ TIMINGAREF_OFFSET
164 ldrne r1, =0x00000618
165 strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET
168 str r1, [r0, #0x034] @ TIMINGROW_OFFSET
169 ldrne r1, =0x182332c8
170 strne r1, [r6, #0x034] @ TIMINGROW_OFFSET
173 str r1, [r0, #0x038] @ TIMINGDATA_OFFSET
174 ldrne r1, =0x13130005
175 strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET
178 str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET
179 ldrne r1, =0x0E180222
180 strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET
184 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
185 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
189 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
190 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
194 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
195 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
197 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
198 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
202 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
203 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
207 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
208 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
212 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
213 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
217 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
218 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
222 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
223 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
225 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
226 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
230 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
231 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
235 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
236 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
238 /* auto refresh on */
239 ldr r1, =0xFF002030 | (1 << 7)
240 str r1, [r0, #0x000] @ CONCONTROL_OFFSET
241 strne r1, [r6, #0x000] @ CONCONTROL_OFFSET
245 str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET
246 strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET
249 str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
250 strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET
252 /* Skip when S5PC110 */
255 /* Check OneDRAM access area at s5pc100 */
256 ldreq r3, =0x38f80222
257 ldreq r1, =0x37ffff00