2 * Copyright (C) 2014 Samsung Electronics
3 * Przemyslaw Marczak <p.marczak@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/pinmux.h>
10 #include <asm/arch/power.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/gpio.h>
14 #include <asm/arch/cpu.h>
15 #include <power/pmic.h>
16 #include <power/max77686_pmic.h>
20 #include <usb/s3c_udc.h>
21 #include <samsung/misc.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #ifdef CONFIG_BOARD_TYPES
27 /* Odroid board types */
34 void set_board_type(void)
36 /* Set GPA1 pin 1 to HI - enable XCL205 output */
37 writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
38 writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
39 writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
40 writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
42 /* Set GPC1 pin 2 to IN - check XCL205 output state */
43 writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
44 writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
46 /* XCL205 - needs some latch time */
49 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
50 if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
51 gd->board_type = ODROID_TYPE_X2;
53 gd->board_type = ODROID_TYPE_U3;
56 const char *get_board_type(void)
58 const char *board_type[] = {"u3", "x2"};
60 return board_type[gd->board_type];
64 #ifdef CONFIG_SET_DFU_ALT_INFO
65 char *get_dfu_alt_system(char *interface, char *devstr)
67 return getenv("dfu_alt_system");
70 char *get_dfu_alt_boot(char *interface, char *devstr)
76 dev_num = simple_strtoul(devstr, NULL, 10);
78 mmc = find_mmc_device(dev_num);
85 alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
86 CONFIG_DFU_ALT_BOOT_EMMC;
92 static void board_clock_init(void)
94 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
95 struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
96 samsung_get_base_clock();
99 * CMU_CPU clocks src to MPLL
101 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
102 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
103 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
104 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
106 clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
107 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
108 set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
109 MUX_MPLL_USER_SEL_C(1);
111 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
113 /* Wait for mux change */
114 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
117 /* Set APLL to 1000MHz */
118 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
119 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
121 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
123 /* Wait for PLL to be locked */
124 while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
127 /* Set CMU_CPU clocks src to APLL */
128 set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
129 MUX_MPLL_USER_SEL_C(1);
130 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
132 /* Wait for mux change */
133 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
136 set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
137 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
138 APLL_RATIO(0) | CORE2_RATIO(0);
140 * Set dividers for MOUTcore = 1000 MHz
141 * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
142 * corem0 = armclk / (ratio + 1) = 333 MHz (2)
143 * corem1 = armclk / (ratio + 1) = 166 MHz (5)
144 * periph = armclk / (ratio + 1) = 1000 MHz (0)
145 * atbout = MOUT / (ratio + 1) = 200 MHz (4)
146 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
147 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
148 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
150 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
151 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
152 APLL_RATIO(7) | CORE2_RATIO(7);
154 clrsetbits_le32(&clk->div_cpu0, clr, set);
156 /* Wait for divider ready status */
157 while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
161 * For MOUThpm = 1000 MHz (MOUTapll)
162 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
163 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
164 * cores_out = armclk / (ratio + 1) = 200 (4)
166 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
167 set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
169 clrsetbits_le32(&clk->div_cpu1, clr, set);
171 /* Wait for divider ready status */
172 while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
176 * Set CMU_DMC clocks src to APLL
178 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
179 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
180 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
181 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
182 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
183 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
184 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
185 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
187 clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
188 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
189 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
190 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
191 set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
192 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
193 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
195 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
197 /* Wait for mux change */
198 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
201 /* Set MPLL to 800MHz */
202 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
204 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
206 /* Wait for PLL to be locked */
207 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
210 /* Switch back CMU_DMC mux */
211 set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
212 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
213 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
215 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
217 /* Wait for mux change */
218 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
222 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
223 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
229 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
230 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
231 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
232 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
233 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
234 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
236 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
237 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
239 clrsetbits_le32(&clk->div_dmc0, clr, set);
241 /* Wait for divider ready status */
242 while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
246 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
247 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
254 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
255 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
256 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
257 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
259 set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
260 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
262 clrsetbits_le32(&clk->div_dmc1, clr, set);
264 /* Wait for divider ready status */
265 while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
269 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
270 UART3_SEL(15) | UART4_SEL(15);
272 * Set CLK_SRC_PERIL0 clocks src to MPLL
273 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
274 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
277 * Set all to SCLK_MPLL_USER_T
279 set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
282 clrsetbits_le32(&clk->src_peril0, clr, set);
285 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
286 UART3_RATIO(15) | UART4_RATIO(15);
288 * For MOUTuart0-4: 800MHz
290 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
292 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
293 UART3_RATIO(7) | UART4_RATIO(7);
295 clrsetbits_le32(&clk->div_peril0, clr, set);
297 while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
301 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
304 * For MOUTmmc0-3 = 800 MHz (MPLL)
306 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
307 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
308 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
309 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
311 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
314 clrsetbits_le32(&clk->div_fsys1, clr, set);
316 /* Wait for divider ready status */
317 while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
321 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
324 * For MOUTmmc0-3 = 800 MHz (MPLL)
326 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
327 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
328 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
329 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
331 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
334 clrsetbits_le32(&clk->div_fsys2, clr, set);
336 /* Wait for divider ready status */
337 while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
341 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
343 * For MOUTmmc4 = 800 MHz (MPLL)
345 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
346 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
348 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
350 clrsetbits_le32(&clk->div_fsys3, clr, set);
352 /* Wait for divider ready status */
353 while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
359 static void board_gpio_init(void)
362 gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
364 gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
365 gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
366 gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
368 /* Enable FAN (Odroid U3) */
369 gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
371 gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
372 gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
373 gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
375 /* OTG Vbus output (Odroid U3+) */
376 gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
378 gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
379 gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
380 gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
382 /* OTG INT (Odroid U3+) */
383 gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
385 gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
386 gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
387 gpio_direction_input(EXYNOS4X12_GPIO_X31);
389 /* Blue LED (Odroid X2/U2/U3) */
390 gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
392 gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
394 #ifdef CONFIG_CMD_USB
395 /* USB3503A Reference frequency */
396 gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
398 /* USB3503A Connect */
399 gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
402 gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
406 static int pmic_init_max77686(void)
408 struct pmic *p = pmic_get("MAX77686_PMIC");
413 /* Set LDO Voltage */
414 max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */
415 max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */
416 max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */
421 int exynos_early_init_f(void)
428 int exynos_init(void)
435 int exynos_power_init(void)
438 pmic_init_max77686();
443 #ifdef CONFIG_USB_GADGET
444 static int s5pc210_phy_control(int on)
448 p_pmic = pmic_get("MAX77686_PMIC");
452 if (pmic_probe(p_pmic))
456 return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
458 return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
461 struct s3c_plat_otg_data s5pc210_otg_data = {
462 .phy_control = s5pc210_phy_control,
463 .regs_phy = EXYNOS4X12_USBPHY_BASE,
464 .regs_otg = EXYNOS4X12_USBOTG_BASE,
465 .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
466 .usb_flags = PHY0_SLEEP,
470 #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
472 int board_usb_init(int index, enum usb_init_type init)
474 #ifdef CONFIG_CMD_USB
477 /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
478 /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
479 if (gd->board_type == ODROID_TYPE_U3)
480 gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
482 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
484 /* Disconnect, Reset, Connect */
485 gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
486 gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
487 gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
488 gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
490 /* Power off and on BUCK8 for LAN9730 */
491 debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
493 p_pmic = pmic_get("MAX77686_PMIC");
494 if (p_pmic && !pmic_probe(p_pmic)) {
495 max77686_set_buck_voltage(p_pmic, 8, 750000);
496 max77686_set_buck_voltage(p_pmic, 8, 3300000);
501 debug("USB_udc_probe\n");
502 return s3c_udc_probe(&s5pc210_otg_data);