2 * Copyright (C) 2014 Samsung Electronics
3 * Przemyslaw Marczak <p.marczak@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/pinmux.h>
10 #include <asm/arch/power.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/gpio.h>
14 #include <asm/arch/cpu.h>
16 #include <power/pmic.h>
17 #include <power/regulator.h>
18 #include <power/max77686_pmic.h>
22 #include <usb/s3c_udc.h>
23 #include <samsung/misc.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_BOARD_TYPES
29 /* Odroid board types */
36 static const char *mmc_regulators[] = {
42 void set_board_type(void)
44 /* Set GPA1 pin 1 to HI - enable XCL205 output */
45 writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
46 writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
47 writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
48 writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
50 /* Set GPC1 pin 2 to IN - check XCL205 output state */
51 writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
52 writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
54 /* XCL205 - needs some latch time */
57 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
58 if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
59 gd->board_type = ODROID_TYPE_X2;
61 gd->board_type = ODROID_TYPE_U3;
64 const char *get_board_type(void)
66 const char *board_type[] = {"u3", "x2"};
68 return board_type[gd->board_type];
72 #ifdef CONFIG_SET_DFU_ALT_INFO
73 char *get_dfu_alt_system(char *interface, char *devstr)
75 return getenv("dfu_alt_system");
78 char *get_dfu_alt_boot(char *interface, char *devstr)
84 dev_num = simple_strtoul(devstr, NULL, 10);
86 mmc = find_mmc_device(dev_num);
93 alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
94 CONFIG_DFU_ALT_BOOT_EMMC;
100 static void board_clock_init(void)
102 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
103 struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
104 samsung_get_base_clock();
107 * CMU_CPU clocks src to MPLL
109 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
110 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
111 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
112 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
114 clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
115 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
116 set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
117 MUX_MPLL_USER_SEL_C(1);
119 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
121 /* Wait for mux change */
122 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
125 /* Set APLL to 1000MHz */
126 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
127 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
129 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
131 /* Wait for PLL to be locked */
132 while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
135 /* Set CMU_CPU clocks src to APLL */
136 set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
137 MUX_MPLL_USER_SEL_C(1);
138 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
140 /* Wait for mux change */
141 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
144 set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
145 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
146 APLL_RATIO(0) | CORE2_RATIO(0);
148 * Set dividers for MOUTcore = 1000 MHz
149 * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
150 * corem0 = armclk / (ratio + 1) = 333 MHz (2)
151 * corem1 = armclk / (ratio + 1) = 166 MHz (5)
152 * periph = armclk / (ratio + 1) = 1000 MHz (0)
153 * atbout = MOUT / (ratio + 1) = 200 MHz (4)
154 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
155 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
156 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
158 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
159 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
160 APLL_RATIO(7) | CORE2_RATIO(7);
162 clrsetbits_le32(&clk->div_cpu0, clr, set);
164 /* Wait for divider ready status */
165 while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
169 * For MOUThpm = 1000 MHz (MOUTapll)
170 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
171 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
172 * cores_out = armclk / (ratio + 1) = 200 (4)
174 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
175 set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
177 clrsetbits_le32(&clk->div_cpu1, clr, set);
179 /* Wait for divider ready status */
180 while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
184 * Set CMU_DMC clocks src to APLL
186 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
187 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
188 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
189 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
190 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
191 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
192 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
193 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
195 clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
196 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
197 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
198 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
199 set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
200 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
201 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
203 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
205 /* Wait for mux change */
206 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
209 /* Set MPLL to 800MHz */
210 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
212 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
214 /* Wait for PLL to be locked */
215 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
218 /* Switch back CMU_DMC mux */
219 set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
220 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
221 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
223 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
225 /* Wait for mux change */
226 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
230 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
231 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
237 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
238 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
239 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
240 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
241 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
242 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
244 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
245 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
247 clrsetbits_le32(&clk->div_dmc0, clr, set);
249 /* Wait for divider ready status */
250 while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
254 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
255 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
262 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
263 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
264 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
265 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
267 set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
268 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
270 clrsetbits_le32(&clk->div_dmc1, clr, set);
272 /* Wait for divider ready status */
273 while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
277 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
278 UART3_SEL(15) | UART4_SEL(15);
280 * Set CLK_SRC_PERIL0 clocks src to MPLL
281 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
282 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
285 * Set all to SCLK_MPLL_USER_T
287 set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
290 clrsetbits_le32(&clk->src_peril0, clr, set);
293 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
294 UART3_RATIO(15) | UART4_RATIO(15);
296 * For MOUTuart0-4: 800MHz
298 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
300 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
301 UART3_RATIO(7) | UART4_RATIO(7);
303 clrsetbits_le32(&clk->div_peril0, clr, set);
305 while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
309 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
312 * For MOUTmmc0-3 = 800 MHz (MPLL)
314 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
315 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
316 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
317 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
319 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
322 clrsetbits_le32(&clk->div_fsys1, clr, set);
324 /* Wait for divider ready status */
325 while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
329 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
332 * For MOUTmmc0-3 = 800 MHz (MPLL)
334 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
335 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
336 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
337 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
339 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
342 clrsetbits_le32(&clk->div_fsys2, clr, set);
344 /* Wait for divider ready status */
345 while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
349 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
351 * For MOUTmmc4 = 800 MHz (MPLL)
353 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
354 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
356 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
358 clrsetbits_le32(&clk->div_fsys3, clr, set);
360 /* Wait for divider ready status */
361 while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
367 static void board_gpio_init(void)
370 gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
372 gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
373 gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
374 gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
376 /* Enable FAN (Odroid U3) */
377 gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
379 gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
380 gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
381 gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
383 /* OTG Vbus output (Odroid U3+) */
384 gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
386 gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
387 gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
388 gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
390 /* OTG INT (Odroid U3+) */
391 gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
393 gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
394 gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
395 gpio_direction_input(EXYNOS4X12_GPIO_X31);
397 /* Blue LED (Odroid X2/U2/U3) */
398 gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
400 gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
402 #ifdef CONFIG_CMD_USB
403 /* USB3503A Reference frequency */
404 gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
406 /* USB3503A Connect */
407 gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
410 gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
414 int exynos_early_init_f(void)
421 int exynos_init(void)
428 int exynos_power_init(void)
430 int list_count = ARRAY_SIZE(mmc_regulators);
432 if (regulator_list_autoset(mmc_regulators, list_count, NULL, true))
433 error("Unable to init all mmc regulators");
438 #ifdef CONFIG_USB_GADGET
439 static int s5pc210_phy_control(int on)
444 ret = regulator_by_platname("VDD_UOTG_3.0V", &dev);
446 error("Regulator get error: %d", ret);
451 return regulator_set_mode(dev, OPMODE_ON);
453 return regulator_set_mode(dev, OPMODE_LPM);
457 struct s3c_plat_otg_data s5pc210_otg_data = {
458 .phy_control = s5pc210_phy_control,
459 .regs_phy = EXYNOS4X12_USBPHY_BASE,
460 .regs_otg = EXYNOS4X12_USBOTG_BASE,
461 .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
462 .usb_flags = PHY0_SLEEP,
466 #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
468 int board_usb_init(int index, enum usb_init_type init)
470 #ifdef CONFIG_CMD_USB
474 /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
475 /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
476 if (gd->board_type == ODROID_TYPE_U3)
477 gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
479 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
481 /* Disconnect, Reset, Connect */
482 gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
483 gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
484 gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
485 gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
487 /* Power off and on BUCK8 for LAN9730 */
488 debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
490 ret = regulator_by_platname("VCC_P3V3_2.85V", &dev);
492 error("Regulator get error: %d", ret);
496 ret = regulator_set_enable(dev, true);
498 error("Regulator %s enable setting error: %d", dev->name, ret);
502 ret = regulator_set_value(dev, 750000);
504 error("Regulator %s value setting error: %d", dev->name, ret);
508 ret = regulator_set_value(dev, 3300000);
510 error("Regulator %s value setting error: %d", dev->name, ret);
514 debug("USB_udc_probe\n");
515 return s3c_udc_probe(&s5pc210_otg_data);