2 * Memory setup for ORIGEN board based on S5PV310
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include "origen_setup.h"
29 .globl mem_ctrl_asm_init
32 * Async bridge configuration at CPU_core:
41 ldr r0, =S5PC210_MIU_BASE
42 /* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
44 str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
46 /* Update MIU Configuration */
48 str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
51 ldr r0, =S5PC210_DMC0_BASE
54 * DLL Parameter Setting:
55 * Termination: Enable R/W
56 * Phase Delay for DQS Cleaning: 180' Shift
59 str r1, [r0, #DMC_PHYCONTROL1]
63 * Termination: Disable
64 * Auto Calibration Start: Enable
67 str r1, [r0, #DMC_PHYZQCONTROL]
75 * Update DLL Information:
76 * Force DLL Resyncronization
79 str r1, [r0, #DMC_PHYCONTROL1]
81 /* Reset Force DLL Resyncronization */
83 str r1, [r0, #DMC_PHYCONTROL1]
85 /* Enable Differential DQS, DLL Off*/
87 str r1, [r0, #DMC_PHYCONTROL0]
89 /* Activate PHY DLL: DLL On */
91 str r1, [r0, #DMC_PHYCONTROL0]
93 /* Set DLL Parameters */
95 str r1, [r0, #DMC_PHYCONTROL1]
99 str r1, [r0, #DMC_PHYCONTROL0]
102 str r1, [r0, #DMC_PHYCONTROL2]
104 /* Set Clock Ratio of Bus clock to Memory Clock */
106 str r1, [r0, #DMC_CONCONTROL]
109 * Memor Burst length: 8
111 * Memory Bus width: 32 bit
113 * Additional Latancy for PLL: 1 Cycle
116 str r1, [r0, #DMC_MEMCONTROL]
119 * Memory Configuration Chip 0
120 * Address Mapping: Interleaved
121 * Number of Column address Bits: 10 bits
122 * Number of Rows Address Bits: 14
126 str r1, [r0, #DMC_MEMCONFIG0]
129 * Memory Configuration Chip 1
130 * Address Mapping: Interleaved
131 * Number of Column address Bits: 10 bits
132 * Number of Rows Address Bits: 14
136 str r1, [r0, #DMC_MEMCONFIG1]
138 /* Config Precharge Policy */
140 str r1, [r0, #DMC_PRECHCONFIG]
143 * TimingAref, TimingRow, TimingData, TimingPower Setting:
144 * Values as per Memory AC Parameters
147 str r1, [r0, #DMC_TIMINGAREF]
149 str r1, [r0, #DMC_TIMINGROW]
151 str r1, [r0, #DMC_TIMINGDATA]
153 str r1, [r0, #DMC_TIMINGPOWER]
155 /* Chip0: NOP Command: Assert and Hold CKE to high level */
157 str r1, [r0, #DMC_DIRECTCMD]
164 /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
166 str r1, [r0, #DMC_DIRECTCMD]
168 str r1, [r0, #DMC_DIRECTCMD]
170 str r1, [r0, #DMC_DIRECTCMD]
172 str r1, [r0, #DMC_DIRECTCMD]
181 str r1, [r0, #DMC_DIRECTCMD]
188 /* Chip1: NOP Command: Assert and Hold CKE to high level */
190 str r1, [r0, #DMC_DIRECTCMD]
197 /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
199 str r1, [r0, #DMC_DIRECTCMD]
201 str r1, [r0, #DMC_DIRECTCMD]
203 str r1, [r0, #DMC_DIRECTCMD]
205 str r1, [r0, #DMC_DIRECTCMD]
214 str r1, [r0, #DMC_DIRECTCMD]
222 str r1, [r0, #DMC_PHYCONTROL1]
224 str r1, [r0, #DMC_PHYCONTROL1]
232 ldr r0, =S5PC210_DMC1_BASE @0x10410000
235 * DLL Parameter Setting:
236 * Termination: Enable R/W
237 * Phase Delay for DQS Cleaning: 180' Shift
240 str r1, [r0, #DMC_PHYCONTROL1]
244 * Termination: Disable
245 * Auto Calibration Start: Enable
248 str r1, [r0, #DMC_PHYZQCONTROL]
256 * Update DLL Information:
257 * Force DLL Resyncronization
260 str r1, [r0, #DMC_PHYCONTROL1]
262 /* Reset Force DLL Resyncronization */
264 str r1, [r0, #DMC_PHYCONTROL1]
266 /* Enable Differential DQS, DLL Off*/
268 str r1, [r0, #DMC_PHYCONTROL0]
270 /* Activate PHY DLL: DLL On */
272 str r1, [r0, #DMC_PHYCONTROL0]
274 /* Set DLL Parameters */
276 str r1, [r0, #DMC_PHYCONTROL1]
280 str r1, [r0, #DMC_PHYCONTROL0]
283 str r1, [r0, #DMC_PHYCONTROL2]
285 /* Set Clock Ratio of Bus clock to Memory Clock */
287 str r1, [r0, #DMC_CONCONTROL]
290 * Memor Burst length: 8
292 * Memory Bus width: 32 bit
294 * Additional Latancy for PLL: 1 Cycle
297 str r1, [r0, #DMC_MEMCONTROL]
300 * Memory Configuration Chip 0
301 * Address Mapping: Interleaved
302 * Number of Column address Bits: 10 bits
303 * Number of Rows Address Bits: 14
307 str r1, [r0, #DMC_MEMCONFIG0]
310 * Memory Configuration Chip 1
311 * Address Mapping: Interleaved
312 * Number of Column address Bits: 10 bits
313 * Number of Rows Address Bits: 14
317 str r1, [r0, #DMC_MEMCONFIG1]
319 /* Config Precharge Policy */
321 str r1, [r0, #DMC_PRECHCONFIG]
324 * TimingAref, TimingRow, TimingData, TimingPower Setting:
325 * Values as per Memory AC Parameters
328 str r1, [r0, #DMC_TIMINGAREF]
330 str r1, [r0, #DMC_TIMINGROW]
332 str r1, [r0, #DMC_TIMINGDATA]
334 str r1, [r0, #DMC_TIMINGPOWER]
336 /* Chip0: NOP Command: Assert and Hold CKE to high level */
338 str r1, [r0, #DMC_DIRECTCMD]
345 /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
347 str r1, [r0, #DMC_DIRECTCMD]
349 str r1, [r0, #DMC_DIRECTCMD]
351 str r1, [r0, #DMC_DIRECTCMD]
353 str r1, [r0, #DMC_DIRECTCMD]
362 str r1, [r0, #DMC_DIRECTCMD]
369 /* Chip1: NOP Command: Assert and Hold CKE to high level */
371 str r1, [r0, #DMC_DIRECTCMD]
378 /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
380 str r1, [r0, #DMC_DIRECTCMD]
382 str r1, [r0, #DMC_DIRECTCMD]
384 str r1, [r0, #DMC_DIRECTCMD]
386 str r1, [r0, #DMC_DIRECTCMD]
395 str r1, [r0, #DMC_DIRECTCMD]
403 str r1, [r0, #DMC_PHYCONTROL1]
405 str r1, [r0, #DMC_PHYCONTROL1]
412 /* turn on DREX0, DREX1 */
413 ldr r0, =S5PC210_DMC0_BASE
415 str r1, [r0, #DMC_CONCONTROL]
417 ldr r0, =S5PC210_DMC1_BASE
419 str r1, [r0, #DMC_CONCONTROL]