2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the Samsung SMDK2410 by
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
11 * SPDX-License-Identifier: GPL-2.0+
17 /* some parameters for the board */
21 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
23 * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
27 #define BWSCON 0x48000000
36 #define B1_BWSCON (DW32)
37 #define B2_BWSCON (DW16)
38 #define B3_BWSCON (DW16 + WAIT + UBLB)
39 #define B4_BWSCON (DW16)
40 #define B5_BWSCON (DW16)
41 #define B6_BWSCON (DW32)
42 #define B7_BWSCON (DW32)
45 #define B0_Tacs 0x0 /* 0clk */
46 #define B0_Tcos 0x0 /* 0clk */
47 #define B0_Tacc 0x7 /* 14clk */
48 #define B0_Tcoh 0x0 /* 0clk */
49 #define B0_Tah 0x0 /* 0clk */
51 #define B0_PMC 0x0 /* normal */
54 #define B1_Tacs 0x0 /* 0clk */
55 #define B1_Tcos 0x0 /* 0clk */
56 #define B1_Tacc 0x7 /* 14clk */
57 #define B1_Tcoh 0x0 /* 0clk */
58 #define B1_Tah 0x0 /* 0clk */
70 #define B3_Tacs 0x0 /* 0clk */
71 #define B3_Tcos 0x3 /* 4clk */
72 #define B3_Tacc 0x7 /* 14clk */
73 #define B3_Tcoh 0x1 /* 1clk */
74 #define B3_Tah 0x0 /* 0clk */
75 #define B3_Tacp 0x3 /* 6clk */
76 #define B3_PMC 0x0 /* normal */
78 #define B4_Tacs 0x0 /* 0clk */
79 #define B4_Tcos 0x0 /* 0clk */
80 #define B4_Tacc 0x7 /* 14clk */
81 #define B4_Tcoh 0x0 /* 0clk */
82 #define B4_Tah 0x0 /* 0clk */
84 #define B4_PMC 0x0 /* normal */
86 #define B5_Tacs 0x0 /* 0clk */
87 #define B5_Tcos 0x0 /* 0clk */
88 #define B5_Tacc 0x7 /* 14clk */
89 #define B5_Tcoh 0x0 /* 0clk */
90 #define B5_Tah 0x0 /* 0clk */
92 #define B5_PMC 0x0 /* normal */
94 #define B6_MT 0x3 /* SDRAM */
96 #define B6_SCAN 0x1 /* 9bit */
98 #define B7_MT 0x3 /* SDRAM */
99 #define B7_Trcd 0x1 /* 3clk */
100 #define B7_SCAN 0x1 /* 9bit */
102 /* REFRESH parameter */
103 #define REFEN 0x1 /* Refresh enable */
104 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
105 #define Trp 0x0 /* 2clk */
106 #define Trc 0x3 /* 7clk */
107 #define Tchr 0x2 /* 3clk */
108 #define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
109 /**************************************/
113 /* memory control configuration */
114 /* make r0 relative the current location so that it */
115 /* reads SMRDATA out of FLASH rather than memory ! */
117 ldr r1, =CONFIG_SYS_TEXT_BASE
119 ldr r1, =BWSCON /* Bus Width Status Controller */
127 /* everything is fine now */
131 /* the literal pools origin */
134 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
135 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
136 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
137 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
138 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
139 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
140 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
141 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
142 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
143 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)