3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * (C) Copyright 2002, 2010
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/s3c24x0_cpu.h>
33 DECLARE_GLOBAL_DATA_PTR;
37 #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
41 #elif FCLK_SPEED==1 /* Fout = 202.8MHz */
59 static inline void pll_delay(unsigned long loops)
61 __asm__ volatile ("1:\n"
63 "bne 1b":"=r" (loops):"0" (loops));
67 * Miscellaneous platform dependent initialisations
70 int board_early_init_f(void)
72 struct s3c24x0_clock_power * const clk_power =
73 s3c24x0_get_base_clock_power();
74 struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
76 /* to reduce PLL lock time, adjust the LOCKTIME register */
77 writel(0xFFFFFF, &clk_power->locktime);
80 writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
83 /* some delay between MPLL and UPLL */
87 writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
90 /* some delay between MPLL and UPLL */
93 /* set up the I/O ports */
94 writel(0x007FFFFF, &gpio->gpacon);
95 writel(0x00044555, &gpio->gpbcon);
96 writel(0x000007FF, &gpio->gpbup);
97 writel(0xAAAAAAAA, &gpio->gpccon);
98 writel(0x0000FFFF, &gpio->gpcup);
99 writel(0xAAAAAAAA, &gpio->gpdcon);
100 writel(0x0000FFFF, &gpio->gpdup);
101 writel(0xAAAAAAAA, &gpio->gpecon);
102 writel(0x0000FFFF, &gpio->gpeup);
103 writel(0x000055AA, &gpio->gpfcon);
104 writel(0x000000FF, &gpio->gpfup);
105 writel(0xFF95FFBA, &gpio->gpgcon);
106 writel(0x0000FFFF, &gpio->gpgup);
107 writel(0x002AFAAA, &gpio->gphcon);
108 writel(0x000007FF, &gpio->gphup);
115 /* arch number of SMDK2410-Board */
116 gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
118 /* adress of boot parameters */
119 gd->bd->bi_boot_params = 0x30000100;
129 /* dram_init must store complete ramsize in gd->ram_size */
130 gd->ram_size = PHYS_SDRAM_1_SIZE;
134 #ifdef CONFIG_CMD_NET
135 int board_eth_init(bd_t *bis)
139 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
146 * Hardcoded flash setup:
147 * Flash 0 is a non-CFI AMD AM29LV800BB flash.
149 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
151 info->portwidth = FLASH_CFI_16BIT;
152 info->chipwidth = FLASH_CFI_BY16;
153 info->interface = FLASH_CFI_X16;