2 * Clock setup for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/clk.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/spl.h>
32 #include "clock_init.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 struct arm_clk_ratios arm_clk_ratios[] = {
47 .pclk_dbg_ratio = 0x1,
62 .pclk_dbg_ratio = 0x1,
77 .pclk_dbg_ratio = 0x1,
92 .pclk_dbg_ratio = 0x1,
107 .pclk_dbg_ratio = 0x1,
114 .arm_freq_mhz = 1700,
122 .pclk_dbg_ratio = 0x1,
130 struct mem_timings mem_timings[] = {
132 .mem_manuf = MEM_MANUF_ELPIDA,
133 .mem_type = DDR_MODE_DDR3,
134 .frequency_mhz = 800,
154 .pclk_cdrex_ratio = 0x5,
156 0x00020018, 0x00030000, 0x00010042, 0x00000d70
158 .timing_ref = 0x000000bb,
159 .timing_row = 0x8c36650e,
160 .timing_data = 0x3630580b,
161 .timing_power = 0x41000a44,
162 .phy0_dqs = 0x08080808,
163 .phy1_dqs = 0x08080808,
164 .phy0_dq = 0x08080808,
165 .phy1_dq = 0x08080808,
168 .phy0_pulld_dqs = 0xf,
169 .phy1_pulld_dqs = 0xf,
171 .lpddr3_ctrl_phy_reset = 0x1,
172 .ctrl_start_point = 0x10,
194 * Dynamic Clock: Always Running
195 * Memory Burst length: 8
197 * Memory Bus width: 32 bit
199 * Additional Latancy for PLL: 0 Cycle
201 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
202 DMC_MEMCONTROL_DPWRDN_DISABLE |
203 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
204 DMC_MEMCONTROL_TP_DISABLE |
205 DMC_MEMCONTROL_DSREF_ENABLE |
206 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
207 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
208 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
209 DMC_MEMCONTROL_NUM_CHIP_1 |
210 DMC_MEMCONTROL_BL_8 |
211 DMC_MEMCONTROL_PZQ_DISABLE |
212 DMC_MEMCONTROL_MRR_BYTE_7_0,
213 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
214 DMC_MEMCONFIGx_CHIP_COL_10 |
215 DMC_MEMCONFIGx_CHIP_ROW_15 |
216 DMC_MEMCONFIGx_CHIP_BANK_8,
217 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
218 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
219 .prechconfig_tp_cnt = 0xff,
222 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
223 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
224 DMC_CONCONTROL_RD_FETCH_DISABLE |
225 DMC_CONCONTROL_EMPTY_DISABLE |
226 DMC_CONCONTROL_AREF_EN_DISABLE |
227 DMC_CONCONTROL_IO_PD_CON_DISABLE,
229 .chips_per_channel = 2,
230 .chips_to_configure = 1,
232 .impedance = IMP_OUTPUT_DRV_30_OHM,
233 .gate_leveling_enable = 0,
235 .mem_manuf = MEM_MANUF_SAMSUNG,
236 .mem_type = DDR_MODE_DDR3,
237 .frequency_mhz = 800,
257 .pclk_cdrex_ratio = 0x5,
259 0x00020018, 0x00030000, 0x00010000, 0x00000d70
261 .timing_ref = 0x000000bb,
262 .timing_row = 0x8c36650e,
263 .timing_data = 0x3630580b,
264 .timing_power = 0x41000a44,
265 .phy0_dqs = 0x08080808,
266 .phy1_dqs = 0x08080808,
267 .phy0_dq = 0x08080808,
268 .phy1_dq = 0x08080808,
271 .phy0_pulld_dqs = 0xf,
272 .phy1_pulld_dqs = 0xf,
274 .lpddr3_ctrl_phy_reset = 0x1,
275 .ctrl_start_point = 0x10,
297 * Dynamic Clock: Always Running
298 * Memory Burst length: 8
300 * Memory Bus width: 32 bit
302 * Additional Latancy for PLL: 0 Cycle
304 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
305 DMC_MEMCONTROL_DPWRDN_DISABLE |
306 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
307 DMC_MEMCONTROL_TP_DISABLE |
308 DMC_MEMCONTROL_DSREF_ENABLE |
309 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
310 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
311 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
312 DMC_MEMCONTROL_NUM_CHIP_1 |
313 DMC_MEMCONTROL_BL_8 |
314 DMC_MEMCONTROL_PZQ_DISABLE |
315 DMC_MEMCONTROL_MRR_BYTE_7_0,
316 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
317 DMC_MEMCONFIGx_CHIP_COL_10 |
318 DMC_MEMCONFIGx_CHIP_ROW_15 |
319 DMC_MEMCONFIGx_CHIP_BANK_8,
320 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
321 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
322 .prechconfig_tp_cnt = 0xff,
325 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
326 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
327 DMC_CONCONTROL_RD_FETCH_DISABLE |
328 DMC_CONCONTROL_EMPTY_DISABLE |
329 DMC_CONCONTROL_AREF_EN_DISABLE |
330 DMC_CONCONTROL_IO_PD_CON_DISABLE,
332 .chips_per_channel = 2,
333 .chips_to_configure = 1,
335 .impedance = IMP_OUTPUT_DRV_40_OHM,
336 .gate_leveling_enable = 1,
341 * Get the required memory type and speed (SPL version).
343 * In SPL we have no device tree, so we use the machine parameters
345 * @param mem_type Returns memory type
346 * @param frequency_mhz Returns memory speed in MHz
347 * @param arm_freq Returns ARM clock speed in MHz
348 * @param mem_manuf Return Memory Manufacturer name
349 * @return 0 if all ok
351 static int clock_get_mem_selection(enum ddr_mode *mem_type,
352 unsigned *frequency_mhz, unsigned *arm_freq,
353 enum mem_manuf *mem_manuf)
355 struct spl_machine_param *params;
357 params = spl_get_machine_params();
358 *mem_type = params->mem_type;
359 *frequency_mhz = params->frequency_mhz;
360 *arm_freq = params->arm_freq_mhz;
361 *mem_manuf = params->mem_manuf;
366 /* Get the ratios for setting ARM clock */
367 struct arm_clk_ratios *get_arm_ratios(void)
369 struct arm_clk_ratios *arm_ratio;
370 enum ddr_mode mem_type;
371 enum mem_manuf mem_manuf;
372 unsigned frequency_mhz, arm_freq;
375 if (clock_get_mem_selection(&mem_type, &frequency_mhz,
376 &arm_freq, &mem_manuf))
378 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
380 if (arm_ratio->arm_freq_mhz == arm_freq)
384 /* will hang if failed to find clock ratio */
391 struct mem_timings *clock_get_mem_timings(void)
393 struct mem_timings *mem;
394 enum ddr_mode mem_type;
395 enum mem_manuf mem_manuf;
396 unsigned frequency_mhz, arm_freq;
399 if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
400 &arm_freq, &mem_manuf)) {
401 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
403 if (mem->mem_type == mem_type &&
404 mem->frequency_mhz == frequency_mhz &&
405 mem->mem_manuf == mem_manuf)
410 /* will hang if failed to find memory timings */
417 void system_clock_init()
419 struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
420 struct mem_timings *mem;
421 struct arm_clk_ratios *arm_clk_ratio;
424 mem = clock_get_mem_timings();
425 arm_clk_ratio = get_arm_ratios();
427 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
429 val = readl(&clk->mux_stat_cpu);
430 } while ((val | MUX_APLL_SEL_MASK) != val);
432 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
434 val = readl(&clk->mux_stat_core1);
435 } while ((val | MUX_MPLL_SEL_MASK) != val);
437 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
438 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
439 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
440 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
441 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
444 val = readl(&clk->mux_stat_top2);
445 } while ((val | tmp) != val);
447 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
449 val = readl(&clk->mux_stat_cdrex);
450 } while ((val | MUX_BPLL_SEL_MASK) != val);
453 writel(APLL_LOCK_VAL, &clk->apll_lock);
455 writel(MPLL_LOCK_VAL, &clk->mpll_lock);
457 writel(BPLL_LOCK_VAL, &clk->bpll_lock);
459 writel(CPLL_LOCK_VAL, &clk->cpll_lock);
461 writel(GPLL_LOCK_VAL, &clk->gpll_lock);
463 writel(EPLL_LOCK_VAL, &clk->epll_lock);
465 writel(VPLL_LOCK_VAL, &clk->vpll_lock);
467 writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
469 writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
471 val = readl(&clk->mux_stat_cpu);
472 } while ((val | HPM_SEL_SCLK_MPLL) != val);
474 val = arm_clk_ratio->arm2_ratio << 28
475 | arm_clk_ratio->apll_ratio << 24
476 | arm_clk_ratio->pclk_dbg_ratio << 20
477 | arm_clk_ratio->atb_ratio << 16
478 | arm_clk_ratio->periph_ratio << 12
479 | arm_clk_ratio->acp_ratio << 8
480 | arm_clk_ratio->cpud_ratio << 4
481 | arm_clk_ratio->arm_ratio;
482 writel(val, &clk->div_cpu0);
484 val = readl(&clk->div_stat_cpu0);
487 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
489 val = readl(&clk->div_stat_cpu1);
493 writel(APLL_CON1_VAL, &clk->apll_con1);
494 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
495 arm_clk_ratio->apll_sdiv);
496 writel(val, &clk->apll_con0);
497 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
501 writel(MPLL_CON1_VAL, &clk->mpll_con1);
502 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
503 writel(val, &clk->mpll_con0);
504 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
508 writel(BPLL_CON1_VAL, &clk->bpll_con1);
509 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
510 writel(val, &clk->bpll_con0);
511 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
515 writel(CPLL_CON1_VAL, &clk->cpll_con1);
516 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
517 writel(val, &clk->cpll_con0);
518 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
522 writel(GPLL_CON1_VAL, &clk->gpll_con1);
523 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
524 writel(val, &clk->gpll_con0);
525 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
529 writel(EPLL_CON2_VAL, &clk->epll_con2);
530 writel(EPLL_CON1_VAL, &clk->epll_con1);
531 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
532 writel(val, &clk->epll_con0);
533 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
537 writel(VPLL_CON2_VAL, &clk->vpll_con2);
538 writel(VPLL_CON1_VAL, &clk->vpll_con1);
539 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
540 writel(val, &clk->vpll_con0);
541 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
544 writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
545 writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
546 while (readl(&clk->div_stat_core0) != 0)
549 writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
550 while (readl(&clk->div_stat_core1) != 0)
553 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
554 while (readl(&clk->div_stat_sysrgt) != 0)
557 writel(CLK_DIV_ACP_VAL, &clk->div_acp);
558 while (readl(&clk->div_stat_acp) != 0)
561 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
562 while (readl(&clk->div_stat_syslft) != 0)
565 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
566 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
567 writel(TOP2_VAL, &clk->src_top2);
568 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
570 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
571 while (readl(&clk->div_stat_top0))
574 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
575 while (readl(&clk->div_stat_top1))
578 writel(CLK_SRC_LEX_VAL, &clk->src_lex);
580 val = readl(&clk->mux_stat_lex);
581 if (val == (val | 1))
585 writel(CLK_DIV_LEX_VAL, &clk->div_lex);
586 while (readl(&clk->div_stat_lex))
589 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
590 while (readl(&clk->div_stat_r0x))
593 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
594 while (readl(&clk->div_stat_r0x))
597 writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
598 while (readl(&clk->div_stat_r1x))
601 writel(CLK_REG_DISABLE, &clk->src_cdrex);
603 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
604 while (readl(&clk->div_stat_cdrex))
607 val = readl(&clk->src_cpu);
608 val |= CLK_SRC_CPU_VAL;
609 writel(val, &clk->src_cpu);
611 val = readl(&clk->src_top2);
612 val |= CLK_SRC_TOP2_VAL;
613 writel(val, &clk->src_top2);
615 val = readl(&clk->src_core1);
616 val |= CLK_SRC_CORE1_VAL;
617 writel(val, &clk->src_core1);
619 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
620 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
621 while (readl(&clk->div_stat_fsys0))
624 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
625 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
626 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
627 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
628 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
629 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
630 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
631 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
633 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
634 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
636 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
637 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
638 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
639 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
641 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
642 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
643 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
644 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
645 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
647 /* FIMD1 SRC CLK SELECTION */
648 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
650 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
651 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
652 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
653 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
654 writel(val, &clk->div_fsys2);
657 void clock_init_dp_clock(void)
659 struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
661 /* DP clock enable */
662 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
664 /* We run DP at 267 Mhz */
665 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);