2 * Clock initialization routines
4 * Copyright (c) 2011 The Chromium OS Authors.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef __EXYNOS_CLOCK_INIT_H
26 #define __EXYNOS_CLOCK_INIT_H
29 MEM_TIMINGS_MSR_COUNT = 4,
32 /* These are the ratio's for configuring ARM clock */
33 struct arm_clk_ratios {
34 unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
42 unsigned pclk_dbg_ratio;
44 unsigned periph_ratio;
50 /* These are the memory timings for a particular memory type and speed */
52 enum mem_manuf mem_manuf; /* Memory manufacturer */
53 enum ddr_mode mem_type; /* Memory type */
54 unsigned frequency_mhz; /* Frequency of memory in MHz */
56 /* Here follow the timing parameters for the selected memory */
78 unsigned pclk_cdrex_ratio;
79 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
84 unsigned timing_power;
86 /* DQS, DQ, DEBUG offsets */
93 unsigned phy0_pulld_dqs;
94 unsigned phy1_pulld_dqs;
96 unsigned lpddr3_ctrl_phy_reset;
97 unsigned ctrl_start_point;
100 unsigned ctrl_dll_on;
105 unsigned ctrl_bstlen;
109 unsigned dfi_init_start;
114 unsigned zq_mode_dds;
115 unsigned zq_mode_term;
116 unsigned zq_mode_noterm; /* 1 to allow termination disable */
121 unsigned membaseconfig0;
122 unsigned membaseconfig1;
123 unsigned prechconfig_tp_cnt;
127 /* Channel and Chip Selection */
128 uint8_t dmc_channels; /* number of memory channels */
129 uint8_t chips_per_channel; /* number of chips per channel */
130 uint8_t chips_to_configure; /* number of chips to configure */
131 uint8_t send_zq_init; /* 1 to send this command */
132 unsigned impedance; /* drive strength impedeance */
133 uint8_t gate_leveling_enable; /* check gate leveling is enabled */
137 * Get the correct memory timings for our selected memory type and speed.
139 * This function can be called from SPL or the main U-Boot.
141 * @return pointer to the memory timings that we should use
143 struct mem_timings *clock_get_mem_timings(void);
146 * Initialize clock for the device
148 void system_clock_init(void);