2 * Mem setup common file for different types of DDR present on SMDK5250 boards.
4 * Copyright (C) 2012 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/spl.h>
28 #include "clock_init.h"
31 #define ZQ_INIT_TIMEOUT 10000
33 int dmc_config_zq(struct mem_timings *mem,
34 struct exynos5_phy_control *phy0_ctrl,
35 struct exynos5_phy_control *phy1_ctrl)
37 unsigned long val = 0;
42 * Select Driver Strength,
43 * long calibration for manual calibration
45 val = PHY_CON16_RESET_VAL;
46 val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
47 val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
49 writel(val, &phy0_ctrl->phy_con16);
50 writel(val, &phy1_ctrl->phy_con16);
52 /* Disable termination */
53 if (mem->zq_mode_noterm)
54 val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
55 writel(val, &phy0_ctrl->phy_con16);
56 writel(val, &phy1_ctrl->phy_con16);
58 /* ZQ_MANUAL_START: Enable */
60 writel(val, &phy0_ctrl->phy_con16);
61 writel(val, &phy1_ctrl->phy_con16);
63 /* ZQ_MANUAL_START: Disable */
64 val &= ~ZQ_MANUAL_STR;
67 * Since we are manaully calibrating the ZQ values,
68 * we are looping for the ZQ_init to complete.
71 while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
77 writel(val, &phy0_ctrl->phy_con16);
80 while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
86 writel(val, &phy1_ctrl->phy_con16);
91 void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
95 if (mode == DDR_MODE_DDR3) {
96 val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
97 writel(val, &dmc->phycontrol0);
100 /* Update DLL Information: Force DLL Resyncronization */
101 val = readl(&dmc->phycontrol0);
103 writel(val, &dmc->phycontrol0);
105 /* Reset Force DLL Resyncronization */
106 val = readl(&dmc->phycontrol0);
108 writel(val, &dmc->phycontrol0);
111 void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
115 for (channel = 0; channel < mem->dmc_channels; channel++) {
118 mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
119 for (chip = 0; chip < mem->chips_to_configure; chip++) {
122 mask |= chip << DIRECT_CMD_CHIP_SHIFT;
124 /* Sending NOP command */
125 writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
128 * TODO(alim.akhtar@samsung.com): Do we need these
129 * delays? This one and the next were not there for
134 /* Sending EMRS/MRS commands */
135 for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
136 writel(mem->direct_cmd_msr[i] | mask,
141 if (mem->send_zq_init) {
142 /* Sending ZQINIT command */
143 writel(DIRECT_CMD_ZQINIT | mask,
152 void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
156 for (channel = 0; channel < mem->dmc_channels; channel++) {
159 mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
160 for (chip = 0; chip < mem->chips_per_channel; chip++) {
161 mask |= chip << DIRECT_CMD_CHIP_SHIFT;
163 /* PALL (all banks precharge) CMD */
164 writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
170 void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
172 writel(mem->memconfig, &dmc->memconfig0);
173 writel(mem->memconfig, &dmc->memconfig1);
174 writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
175 writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
180 struct spl_machine_param *param = spl_get_machine_params();
181 struct mem_timings *mem;
184 mem = clock_get_mem_timings();
186 /* If there are any other memory variant, add their init call below */
187 if (param->mem_type == DDR_MODE_DDR3) {
188 ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
190 /* will hang if failed to init memory control */
195 /* will hang if unknow memory type */