2 * Copyright (C) 2012 Samsung Electronics
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/dwmmc.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/mmc.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/power.h>
21 #include <asm/arch/sromc.h>
22 #include <power/pmic.h>
23 #include <power/max77686_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #if defined CONFIG_EXYNOS_TMU
30 * Boot Time Thermal Analysis for SoC temperature threshold breach
32 static void boot_temp_check(void)
36 switch (tmu_monitor(&temp)) {
37 /* Status TRIPPED ans WARNING means corresponding threshold breach */
38 case TMU_STATUS_TRIPPED:
39 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
43 case TMU_STATUS_WARNING:
44 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
47 * TMU_STATUS_INIT means something is wrong with temperature sensing
48 * and TMU status was changed back from NORMAL to INIT.
52 debug("EXYNOS_TMU: Unknown TMU state\n");
58 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
59 int cros_ec_err; /* Error for cros_ec, 0 if ok */
62 static struct local_info local;
64 #ifdef CONFIG_SOUND_MAX98095
65 static void board_enable_audio_codec(void)
67 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
68 samsung_get_base_gpio_part1();
70 /* Enable MAX98095 Codec */
71 s5p_gpio_direction_output(&gpio1->x1, 7, 1);
72 s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
76 struct cros_ec_dev *board_get_cros_ec_dev(void)
78 return local.cros_ec_dev;
81 static int board_init_cros_ec_devices(const void *blob)
83 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
84 if (local.cros_ec_err)
85 return -1; /* Will report in board_late_init() */
92 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
94 #if defined CONFIG_EXYNOS_TMU
95 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
96 debug("%s: Failed to init TMU\n", __func__);
102 #ifdef CONFIG_EXYNOS_SPI
106 if (board_init_cros_ec_devices(gd->fdt_blob))
109 #ifdef CONFIG_SOUND_MAX98095
110 board_enable_audio_codec();
120 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
121 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
122 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
127 #if defined(CONFIG_POWER)
128 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
133 ret = pmic_reg_read(p, reg, &val);
135 debug("%s: PMIC %d register read failed\n", __func__, reg);
139 ret = pmic_reg_write(p, reg, val);
141 debug("%s: PMIC %d register write failed\n", __func__, reg);
147 int power_init_board(void)
153 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
155 if (pmic_init(I2C_PMIC))
158 p = pmic_get("MAX77686_PMIC");
165 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
168 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
169 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
173 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
174 MAX77686_BUCK1OUT_1V)) {
175 debug("%s: PMIC %d register write failed\n", __func__,
176 MAX77686_REG_PMIC_BUCK1OUT);
180 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
181 MAX77686_BUCK1CTRL_EN))
185 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
186 MAX77686_BUCK2DVS1_1_3V)) {
187 debug("%s: PMIC %d register write failed\n", __func__,
188 MAX77686_REG_PMIC_BUCK2DVS1);
192 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
193 MAX77686_BUCK2CTRL_ON))
197 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
198 MAX77686_BUCK3DVS1_1_0125V)) {
199 debug("%s: PMIC %d register write failed\n", __func__,
200 MAX77686_REG_PMIC_BUCK3DVS1);
204 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
205 MAX77686_BUCK3CTRL_ON))
209 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
210 MAX77686_BUCK4DVS1_1_2V)) {
211 debug("%s: PMIC %d register write failed\n", __func__,
212 MAX77686_REG_PMIC_BUCK4DVS1);
216 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
217 MAX77686_BUCK3CTRL_ON))
221 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
222 MAX77686_LD02CTRL1_1_5V | EN_LDO))
226 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
227 MAX77686_LD03CTRL1_1_8V | EN_LDO))
231 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
232 MAX77686_LD05CTRL1_1_8V | EN_LDO))
236 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
237 MAX77686_LD10CTRL1_1_8V | EN_LDO))
244 void dram_init_banksize(void)
249 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
250 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
251 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
253 gd->bd->bi_dram[i].start = addr;
254 gd->bd->bi_dram[i].size = size;
258 static int decode_sromc(const void *blob, struct fdt_sromc *config)
263 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
265 debug("Could not find SROMC node\n");
269 config->bank = fdtdec_get_int(blob, node, "bank", 0);
270 config->width = fdtdec_get_int(blob, node, "width", 2);
272 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
273 FDT_SROM_TIMING_COUNT);
275 debug("Could not decode SROMC configuration Error: %s\n",
277 return -FDT_ERR_NOTFOUND;
282 int board_eth_init(bd_t *bis)
284 #ifdef CONFIG_SMC911X
285 u32 smc_bw_conf, smc_bc_conf;
286 struct fdt_sromc config;
287 fdt_addr_t base_addr;
290 node = decode_sromc(gd->fdt_blob, &config);
292 debug("%s: Could not find sromc configuration\n", __func__);
295 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
297 debug("%s: Could not find lan9215 configuration\n", __func__);
301 /* We now have a node, so any problems from now on are errors */
302 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
303 if (base_addr == FDT_ADDR_T_NONE) {
304 debug("%s: Could not find lan9215 address\n", __func__);
308 /* Ethernet needs data bus width of 16 bits */
309 if (config.width != 2) {
310 debug("%s: Unsupported bus width %d\n", __func__,
314 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
315 | SROMC_BYTE_ENABLE(config.bank);
317 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
318 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
319 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
320 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
321 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
322 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
323 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
325 /* Select and configure the SROMC bank */
326 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
327 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
328 return smc911x_initialize(0, base_addr);
333 #ifdef CONFIG_DISPLAY_BOARDINFO
336 const char *board_name;
338 board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
339 if (board_name == NULL)
340 printf("\nUnknown Board\n");
342 printf("\nBoard: %s\n", board_name);
348 #ifdef CONFIG_GENERIC_MMC
349 int board_mmc_init(bd_t *bis)
352 /* dwmmc initializattion for available channels */
353 ret = exynos_dwmmc_init(gd->fdt_blob);
355 debug("dwmmc init failed\n");
361 static int board_uart_init(void)
363 int err, uart_id, ret = 0;
365 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
366 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
368 debug("UART%d not configured\n",
369 (uart_id - PERIPH_ID_UART0));
376 #ifdef CONFIG_BOARD_EARLY_INIT_F
377 int board_early_init_f(void)
380 err = board_uart_init();
382 debug("UART init failed\n");
385 #ifdef CONFIG_SYS_I2C_INIT_BOARD
386 board_i2c_init(gd->fdt_blob);
393 void exynos_cfg_lcd_gpio(void)
395 struct exynos5_gpio_part1 *gpio1 =
396 (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
399 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
400 s5p_gpio_set_value(&gpio1->b2, 0, 1);
403 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
404 s5p_gpio_set_value(&gpio1->x1, 5, 1);
406 /* Set Hotplug detect for DP */
407 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
410 void exynos_set_dp_phy(unsigned int onoff)
412 set_dp_phy_ctrl(onoff);
416 #ifdef CONFIG_BOARD_LATE_INIT
417 int board_late_init(void)
419 stdio_print_current_devices();
421 if (local.cros_ec_err) {
422 /* Force console on */
423 gd->flags &= ~GD_FLG_SILENT;
425 printf("cros-ec communications failure %d\n",
427 puts("\nPlease reset with Power+Refresh\n\n");
428 panic("Cannot init cros-ec device");