2 * Copyright (C) 2012 Samsung Electronics
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/dwmmc.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/mmc.h>
34 #include <asm/arch/pinmux.h>
35 #include <asm/arch/power.h>
36 #include <asm/arch/sromc.h>
37 #include <power/pmic.h>
38 #include <power/max77686_pmic.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #if defined CONFIG_EXYNOS_TMU
45 * Boot Time Thermal Analysis for SoC temperature threshold breach
47 static void boot_temp_check(void)
51 switch (tmu_monitor(&temp)) {
52 /* Status TRIPPED ans WARNING means corresponding threshold breach */
53 case TMU_STATUS_TRIPPED:
54 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
58 case TMU_STATUS_WARNING:
59 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
62 * TMU_STATUS_INIT means something is wrong with temperature sensing
63 * and TMU status was changed back from NORMAL to INIT.
67 debug("EXYNOS_TMU: Unknown TMU state\n");
72 #ifdef CONFIG_USB_EHCI_EXYNOS
73 int board_usb_vbus_init(void)
75 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
76 samsung_get_base_gpio_part1();
78 /* Enable VBUS power switch */
79 s5p_gpio_direction_output(&gpio1->x2, 6, 1);
81 /* VBUS turn ON time */
88 #ifdef CONFIG_SOUND_MAX98095
89 static void board_enable_audio_codec(void)
91 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
92 samsung_get_base_gpio_part1();
94 /* Enable MAX98095 Codec */
95 s5p_gpio_direction_output(&gpio1->x1, 7, 1);
96 s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
102 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
104 #if defined CONFIG_EXYNOS_TMU
105 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
106 debug("%s: Failed to init TMU\n", __func__);
112 #ifdef CONFIG_EXYNOS_SPI
115 #ifdef CONFIG_USB_EHCI_EXYNOS
116 board_usb_vbus_init();
118 #ifdef CONFIG_SOUND_MAX98095
119 board_enable_audio_codec();
129 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
130 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
131 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
136 #if defined(CONFIG_POWER)
137 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
142 ret = pmic_reg_read(p, reg, &val);
144 debug("%s: PMIC %d register read failed\n", __func__, reg);
148 ret = pmic_reg_write(p, reg, val);
150 debug("%s: PMIC %d register write failed\n", __func__, reg);
156 int power_init_board(void)
162 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
164 if (pmic_init(I2C_PMIC))
167 p = pmic_get("MAX77686_PMIC");
174 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
177 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
178 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
182 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
183 MAX77686_BUCK1OUT_1V)) {
184 debug("%s: PMIC %d register write failed\n", __func__,
185 MAX77686_REG_PMIC_BUCK1OUT);
189 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
190 MAX77686_BUCK1CTRL_EN))
194 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
195 MAX77686_BUCK2DVS1_1_3V)) {
196 debug("%s: PMIC %d register write failed\n", __func__,
197 MAX77686_REG_PMIC_BUCK2DVS1);
201 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
202 MAX77686_BUCK2CTRL_ON))
206 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
207 MAX77686_BUCK3DVS1_1_0125V)) {
208 debug("%s: PMIC %d register write failed\n", __func__,
209 MAX77686_REG_PMIC_BUCK3DVS1);
213 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
214 MAX77686_BUCK3CTRL_ON))
218 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
219 MAX77686_BUCK4DVS1_1_2V)) {
220 debug("%s: PMIC %d register write failed\n", __func__,
221 MAX77686_REG_PMIC_BUCK4DVS1);
225 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
226 MAX77686_BUCK3CTRL_ON))
230 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
231 MAX77686_LD02CTRL1_1_5V | EN_LDO))
235 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
236 MAX77686_LD03CTRL1_1_8V | EN_LDO))
240 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
241 MAX77686_LD05CTRL1_1_8V | EN_LDO))
245 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
246 MAX77686_LD10CTRL1_1_8V | EN_LDO))
253 void dram_init_banksize(void)
258 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
259 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
260 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
262 gd->bd->bi_dram[i].start = addr;
263 gd->bd->bi_dram[i].size = size;
267 static int decode_sromc(const void *blob, struct fdt_sromc *config)
272 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
274 debug("Could not find SROMC node\n");
278 config->bank = fdtdec_get_int(blob, node, "bank", 0);
279 config->width = fdtdec_get_int(blob, node, "width", 2);
281 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
282 FDT_SROM_TIMING_COUNT);
284 debug("Could not decode SROMC configuration Error: %s\n",
286 return -FDT_ERR_NOTFOUND;
291 int board_eth_init(bd_t *bis)
293 #ifdef CONFIG_SMC911X
294 u32 smc_bw_conf, smc_bc_conf;
295 struct fdt_sromc config;
296 fdt_addr_t base_addr;
299 node = decode_sromc(gd->fdt_blob, &config);
301 debug("%s: Could not find sromc configuration\n", __func__);
304 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
306 debug("%s: Could not find lan9215 configuration\n", __func__);
310 /* We now have a node, so any problems from now on are errors */
311 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
312 if (base_addr == FDT_ADDR_T_NONE) {
313 debug("%s: Could not find lan9215 address\n", __func__);
317 /* Ethernet needs data bus width of 16 bits */
318 if (config.width != 2) {
319 debug("%s: Unsupported bus width %d\n", __func__,
323 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
324 | SROMC_BYTE_ENABLE(config.bank);
326 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
327 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
328 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
329 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
330 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
331 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
332 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
334 /* Select and configure the SROMC bank */
335 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
336 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
337 return smc911x_initialize(0, base_addr);
342 #ifdef CONFIG_DISPLAY_BOARDINFO
345 const char *board_name;
347 board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
348 if (board_name == NULL)
349 printf("\nUnknown Board\n");
351 printf("\nBoard: %s\n", board_name);
357 #ifdef CONFIG_GENERIC_MMC
358 int board_mmc_init(bd_t *bis)
361 /* dwmmc initializattion for available channels */
362 ret = exynos_dwmmc_init(gd->fdt_blob);
364 debug("dwmmc init failed\n");
370 static int board_uart_init(void)
372 int err, uart_id, ret = 0;
374 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
375 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
377 debug("UART%d not configured\n",
378 (uart_id - PERIPH_ID_UART0));
385 #ifdef CONFIG_BOARD_EARLY_INIT_F
386 int board_early_init_f(void)
389 err = board_uart_init();
391 debug("UART init failed\n");
394 #ifdef CONFIG_SYS_I2C_INIT_BOARD
395 board_i2c_init(gd->fdt_blob);
402 void exynos_cfg_lcd_gpio(void)
404 struct exynos5_gpio_part1 *gpio1 =
405 (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
408 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
409 s5p_gpio_set_value(&gpio1->b2, 0, 1);
412 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
413 s5p_gpio_set_value(&gpio1->x1, 5, 1);
415 /* Set Hotplug detect for DP */
416 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
419 void exynos_set_dp_phy(unsigned int onoff)
421 set_dp_phy_ctrl(onoff);