2 * Copyright (C) 2012 Samsung Electronics
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/dwmmc.h>
17 #include <asm/arch/mmc.h>
18 #include <asm/arch/pinmux.h>
19 #include <asm/arch/power.h>
20 #include <asm/arch/sromc.h>
21 #include <power/pmic.h>
22 #include <power/max77686_pmic.h>
23 #include <power/tps65090_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_SOUND_MAX98095
29 static void board_enable_audio_codec(void)
31 /* Enable MAX98095 Codec */
32 gpio_direction_output(EXYNOS5_GPIO_X17, 1);
33 gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
39 #ifdef CONFIG_SOUND_MAX98095
40 board_enable_audio_codec();
45 #if defined(CONFIG_POWER)
46 #ifdef CONFIG_POWER_MAX77686
47 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
52 ret = pmic_reg_read(p, reg, &val);
54 debug("%s: PMIC %d register read failed\n", __func__, reg);
58 ret = pmic_reg_write(p, reg, val);
60 debug("%s: PMIC %d register write failed\n", __func__, reg);
66 static int max77686_init(void)
70 if (pmic_init(I2C_PMIC))
73 p = pmic_get("MAX77686_PMIC");
80 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
83 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
84 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
88 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
89 MAX77686_BUCK1OUT_1V)) {
90 debug("%s: PMIC %d register write failed\n", __func__,
91 MAX77686_REG_PMIC_BUCK1OUT);
95 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
96 MAX77686_BUCK1CTRL_EN))
100 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
101 MAX77686_BUCK2DVS1_1_3V)) {
102 debug("%s: PMIC %d register write failed\n", __func__,
103 MAX77686_REG_PMIC_BUCK2DVS1);
107 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
108 MAX77686_BUCK2CTRL_ON))
112 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
113 MAX77686_BUCK3DVS1_1_0125V)) {
114 debug("%s: PMIC %d register write failed\n", __func__,
115 MAX77686_REG_PMIC_BUCK3DVS1);
119 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
120 MAX77686_BUCK3CTRL_ON))
124 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
125 MAX77686_BUCK4DVS1_1_2V)) {
126 debug("%s: PMIC %d register write failed\n", __func__,
127 MAX77686_REG_PMIC_BUCK4DVS1);
131 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
132 MAX77686_BUCK3CTRL_ON))
136 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
137 MAX77686_LD02CTRL1_1_5V | EN_LDO))
141 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
142 MAX77686_LD03CTRL1_1_8V | EN_LDO))
146 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
147 MAX77686_LD05CTRL1_1_8V | EN_LDO))
151 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
152 MAX77686_LD10CTRL1_1_8V | EN_LDO))
157 #endif /* CONFIG_POWER_MAX77686 */
159 int exynos_power_init(void)
163 #ifdef CONFIG_POWER_MAX77686
164 ret = max77686_init();
168 #ifdef CONFIG_POWER_TPS65090
170 * The TPS65090 may not be in the device tree. If so, it is not
173 ret = tps65090_init();
174 if (ret == 0 || ret == -ENODEV)
180 #endif /* CONFIG_POWER */
183 static int board_dp_bridge_setup(void)
185 const int max_tries = 10;
189 * TODO(sjg): Use device tree for GPIOs when exynos GPIO
190 * numbering patch is in mainline.
192 debug("%s\n", __func__);
193 node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460);
195 debug("%s: No node for DP bridge in device tree\n", __func__);
199 /* Setup the GPIOs */
201 /* PD is ACTIVE_LOW, and initially de-asserted */
202 gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE);
203 gpio_direction_output(EXYNOS5_GPIO_Y25, 1);
205 /* Reset is ACTIVE_LOW */
206 gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE);
207 gpio_direction_output(EXYNOS5_GPIO_X15, 0);
210 gpio_set_value(EXYNOS5_GPIO_X15, 1);
212 gpio_direction_input(EXYNOS5_GPIO_X07);
215 * We need to wait for 90ms after bringing up the bridge since there
216 * is a phantom "high" on the HPD chip during its bootup. The phantom
217 * high comes within 7ms of de-asserting PD and persists for at least
218 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
219 * phantom high makes it hard for us to know when the NXP chip is up.
223 for (num_tries = 0; num_tries < max_tries; num_tries++) {
224 /* Check HPD. If it's high, we're all good. */
225 if (gpio_get_value(EXYNOS5_GPIO_X07))
228 debug("%s: eDP bridge failed to come up; try %d of %d\n",
229 __func__, num_tries, max_tries);
232 /* Immediately go into bridge reset if the hp line is not high */
236 void exynos_cfg_lcd_gpio(void)
239 gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
240 gpio_set_value(EXYNOS5_GPIO_B20, 1);
243 gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
244 gpio_set_value(EXYNOS5_GPIO_X15, 1);
246 /* Set Hotplug detect for DP */
247 gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
250 void exynos_set_dp_phy(unsigned int onoff)
252 set_dp_phy_ctrl(onoff);
255 void exynos_backlight_on(unsigned int on)
257 debug("%s(%u)\n", __func__, on);
262 #ifdef CONFIG_POWER_TPS65090
265 ret = tps65090_fet_enable(1); /* Enable FET1, backlight */
269 /* T5 in the LCD timing spec (defined as > 10ms) */
272 /* board_dp_backlight_pwm */
273 gpio_direction_output(EXYNOS5_GPIO_B20, 1);
275 /* T6 in the LCD timing spec (defined as > 10ms) */
278 /* board_dp_backlight_en */
279 gpio_direction_output(EXYNOS5_GPIO_X30, 1);
283 void exynos_lcd_power_on(void)
287 debug("%s\n", __func__);
289 #ifdef CONFIG_POWER_TPS65090
290 /* board_dp_lcd_vdd */
291 tps65090_fet_enable(6); /* Enable FET6, lcd panel */
294 ret = board_dp_bridge_setup();
295 if (ret && ret != -ENODEV)
296 printf("LCD bridge failed to enable: %d\n", ret);