git.sur5r.net Git - u-boot/blob - board/samsung/smdk5250/setup.h

   1 /*
   2  * Machine Specific Values for SMDK5250 board based on S5PC520
   3  *
   4  * Copyright (C) 2012 Samsung Electronics
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _SMDK5250_SETUP_H
  26 #define _SMDK5250_SETUP_H
  27
  28 #include <config.h>
  29 #include <version.h>
  30 #include <asm/arch/cpu.h>
  31
  32 /* GPIO Offsets for UART: GPIO Contol Register */
  33 #define EXYNOS5_GPIO_A0_CON_OFFSET      0x0
  34 #define EXYNOS5_GPIO_A1_CON_OFFSET      0x20
  35
  36 /* TZPC : Register Offsets */
  37 #define TZPC0_BASE              0x10100000
  38 #define TZPC1_BASE              0x10110000
  39 #define TZPC2_BASE              0x10120000
  40 #define TZPC3_BASE              0x10130000
  41 #define TZPC4_BASE              0x10140000
  42 #define TZPC5_BASE              0x10150000
  43 #define TZPC6_BASE              0x10160000
  44 #define TZPC7_BASE              0x10170000
  45 #define TZPC8_BASE              0x10180000
  46 #define TZPC9_BASE              0x10190000
  47
  48 /* CLK_SRC_CPU */
  49 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
  50 #define MUX_HPM_SEL             0
  51 #define MUX_CPU_SEL             0
  52 #define MUX_APLL_SEL            1
  53 #define CLK_SRC_CPU_VAL         ((MUX_HPM_SEL << 20) \
  54                                 | (MUX_CPU_SEL << 16) \
  55                                 | (MUX_APLL_SEL))
  56
  57 /* CLK_DIV_CPU0 */
  58 #define ARM2_RATIO              0x0
  59 #define APLL_RATIO              0x1
  60 #define PCLK_DBG_RATIO          0x1
  61 #define ATB_RATIO               0x4
  62 #define PERIPH_RATIO            0x7
  63 #define ACP_RATIO               0x7
  64 #define CPUD_RATIO              0x2
  65 #define ARM_RATIO               0x0
  66 #define CLK_DIV_CPU0_VAL        ((ARM2_RATIO << 28) \
  67                                 | (APLL_RATIO << 24) \
  68                                 | (PCLK_DBG_RATIO << 20) \
  69                                 | (ATB_RATIO << 16) \
  70                                 | (PERIPH_RATIO << 12) \
  71                                 | (ACP_RATIO << 8) \
  72                                 | (CPUD_RATIO << 4) \
  73                                 | (ARM_RATIO))
  74
  75 /* CLK_DIV_CPU1 */
  76 #define HPM_RATIO               0x4
  77 #define COPY_RATIO              0x0
  78 #define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4) \
  79                                 | (COPY_RATIO))
  80
  81 #define APLL_MDIV               0x7D
  82 #define APLL_PDIV               0x3
  83 #define APLL_SDIV               0x0
  84
  85 #define MPLL_MDIV               0x64
  86 #define MPLL_PDIV               0x3
  87 #define MPLL_SDIV               0x0
  88
  89 #define CPLL_MDIV               0x96
  90 #define CPLL_PDIV               0x4
  91 #define CPLL_SDIV               0x0
  92
  93 /* APLL_CON1 */
  94 #define APLL_CON1_VAL   (0x00203800)
  95
  96 /* MPLL_CON1 */
  97 #define MPLL_CON1_VAL   (0x00203800)
  98
  99 /* CPLL_CON1 */
 100 #define CPLL_CON1_VAL   (0x00203800)
 101
 102 #define EPLL_MDIV       0x60
 103 #define EPLL_PDIV       0x3
 104 #define EPLL_SDIV       0x3
 105
 106 #define EPLL_CON1_VAL   0x00000000
 107 #define EPLL_CON2_VAL   0x00000080
 108
 109 #define VPLL_MDIV       0x96
 110 #define VPLL_PDIV       0x3
 111 #define VPLL_SDIV       0x2
 112
 113 #define VPLL_CON1_VAL   0x00000000
 114 #define VPLL_CON2_VAL   0x00000080
 115
 116 #define BPLL_MDIV       0x215
 117 #define BPLL_PDIV       0xC
 118 #define BPLL_SDIV       0x1
 119
 120 #define BPLL_CON1_VAL   0x00203800
 121
 122 /* Set PLL */
 123 #define set_pll(mdiv, pdiv, sdiv)       (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
 124
 125 #define APLL_CON0_VAL   set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
 126 #define MPLL_CON0_VAL   set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
 127 #define CPLL_CON0_VAL   set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
 128 #define EPLL_CON0_VAL   set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
 129 #define VPLL_CON0_VAL   set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
 130 #define BPLL_CON0_VAL   set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
 131
 132 /* CLK_SRC_CORE0 */
 133 #define CLK_SRC_CORE0_VAL       0x00060000
 134
 135 /* CLK_SRC_CORE1 */
 136 #define CLK_SRC_CORE1_VAL       0x100
 137
 138 /* CLK_DIV_CORE0 */
 139 #define CLK_DIV_CORE0_VAL       0x120000
 140
 141 /* CLK_DIV_CORE1 */
 142 #define CLK_DIV_CORE1_VAL       0x07070700
 143
 144 /* CLK_SRC_CDREX */
 145 #define CLK_SRC_CDREX_INIT_VAL  0x1
 146 #define CLK_SRC_CDREX_VAL       0x111
 147
 148 /* CLK_DIV_CDREX */
 149 #define CLK_DIV_CDREX_INIT_VAL  0x71771111
 150
 151 #define MCLK_CDREX2_RATIO       0x0
 152 #define ACLK_EFCON_RATIO        0x1
 153 #define MCLK_DPHY_RATIO         0x0
 154 #define MCLK_CDREX_RATIO        0x0
 155 #define ACLK_C2C_200_RATIO      0x1
 156 #define C2C_CLK_400_RATIO       0x1
 157 #define PCLK_CDREX_RATIO        0x3
 158 #define ACLK_CDREX_RATIO        0x1
 159 #define CLK_DIV_CDREX_VAL       ((MCLK_DPHY_RATIO << 20) \
 160                                 | (MCLK_CDREX_RATIO << 16) \
 161                                 | (ACLK_C2C_200_RATIO << 12) \
 162                                 | (C2C_CLK_400_RATIO << 8) \
 163                                 | (PCLK_CDREX_RATIO << 4) \
 164                                 | (ACLK_CDREX_RATIO))
 165
 166 #define MCLK_EFPHY_RATIO        0x4
 167 #define CLK_DIV_CDREX2_VAL      MCLK_EFPHY_RATIO
 168
 169 /* CLK_DIV_ACP */
 170 #define CLK_DIV_ACP_VAL 0x12
 171
 172 /* CLK_SRC_TOP0 */
 173 #define MUX_ACLK_300_GSCL_SEL           0x1
 174 #define MUX_ACLK_300_GSCL_MID_SEL       0x0
 175 #define MUX_ACLK_400_SEL                0x0
 176 #define MUX_ACLK_333_SEL                0x0
 177 #define MUX_ACLK_300_DISP1_SEL          0x1
 178 #define MUX_ACLK_300_DISP1_MID_SEL      0x0
 179 #define MUX_ACLK_200_SEL                0x0
 180 #define MUX_ACLK_166_SEL                0x0
 181 #define CLK_SRC_TOP0_VAL        ((MUX_ACLK_300_GSCL_SEL << 25) \
 182                                 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
 183                                 | (MUX_ACLK_400_SEL << 20) \
 184                                 | (MUX_ACLK_333_SEL << 16) \
 185                                 | (MUX_ACLK_300_DISP1_SEL << 15) \
 186                                 | (MUX_ACLK_300_DISP1_MID_SEL << 14)    \
 187                                 | (MUX_ACLK_200_SEL << 12) \
 188                                 | (MUX_ACLK_166_SEL << 8))
 189
 190 /* CLK_SRC_TOP1 */
 191 #define MUX_ACLK_400_ISP_SEL            0x0
 192 #define MUX_ACLK_400_IOP_SEL            0x0
 193 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL    0x0
 194 #define CLK_SRC_TOP1_VAL                ((MUX_ACLK_400_ISP_SEL << 24) \
 195                                         |(MUX_ACLK_400_IOP_SEL << 20) \
 196                                         |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
 197
 198 /* CLK_SRC_TOP2 */
 199 #define MUX_BPLL_USER_SEL       0x1
 200 #define MUX_MPLL_USER_SEL       0x1
 201 #define MUX_VPLL_SEL            0x0
 202 #define MUX_EPLL_SEL            0x0
 203 #define MUX_CPLL_SEL            0x0
 204 #define VPLLSRC_SEL             0x0
 205 #define CLK_SRC_TOP2_VAL        ((MUX_BPLL_USER_SEL << 24) \
 206                                 | (MUX_MPLL_USER_SEL << 20) \
 207                                 | (MUX_VPLL_SEL << 16) \
 208                                 | (MUX_EPLL_SEL << 12) \
 209                                 | (MUX_CPLL_SEL << 8) \
 210                                 | (VPLLSRC_SEL))
 211 /* CLK_SRC_TOP3 */
 212 #define MUX_ACLK_333_SUB_SEL            0x1
 213 #define MUX_ACLK_400_SUB_SEL            0x1
 214 #define MUX_ACLK_266_ISP_SUB_SEL        0x1
 215 #define MUX_ACLK_266_GPS_SUB_SEL        0x1
 216 #define MUX_ACLK_300_GSCL_SUB_SEL       0x1
 217 #define MUX_ACLK_266_GSCL_SUB_SEL       0x1
 218 #define MUX_ACLK_300_DISP1_SUB_SEL      0x1
 219 #define MUX_ACLK_200_DISP1_SUB_SEL      0x1
 220 #define CLK_SRC_TOP3_VAL                ((MUX_ACLK_333_SUB_SEL << 24) \
 221                                         | (MUX_ACLK_400_SUB_SEL << 20) \
 222                                         | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
 223                                         | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
 224                                         | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
 225                                         | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
 226                                         | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
 227                                         | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
 228
 229 /* CLK_DIV_TOP0 */
 230 #define ACLK_300_RATIO          0x0
 231 #define ACLK_400_RATIO          0x3
 232 #define ACLK_333_RATIO          0x2
 233 #define ACLK_266_RATIO          0x2
 234 #define ACLK_200_RATIO          0x3
 235 #define ACLK_166_RATIO          0x5
 236 #define ACLK_133_RATIO          0x1
 237 #define ACLK_66_RATIO           0x5
 238 #define CLK_DIV_TOP0_VAL        ((ACLK_300_RATIO << 28) \
 239                                 | (ACLK_400_RATIO << 24) \
 240                                 | (ACLK_333_RATIO << 20) \
 241                                 | (ACLK_266_RATIO << 16) \
 242                                 | (ACLK_200_RATIO << 12) \
 243                                 | (ACLK_166_RATIO << 8) \
 244                                 | (ACLK_133_RATIO << 4) \
 245                                 | (ACLK_66_RATIO))
 246
 247 /* CLK_DIV_TOP1 */
 248 #define ACLK_MIPI_HSI_TX_BASE_RATIO     0x3
 249 #define ACLK_66_PRE_RATIO       0x1
 250 #define ACLK_400_ISP_RATIO      0x1
 251 #define ACLK_400_IOP_RATIO      0x1
 252 #define ACLK_300_GSCL_RATIO     0x0
 253 #define ACLK_266_GPS_RATIO      0x7
 254
 255 #define CLK_DIV_TOP1_VAL        ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
 256                                 | (ACLK_66_PRE_RATIO << 24) \
 257                                 | (ACLK_400_ISP_RATIO << 20) \
 258                                 | (ACLK_400_IOP_RATIO << 16) \
 259                                 | (ACLK_300_GSCL_RATIO << 12) \
 260                                 | (ACLK_266_GPS_RATIO << 8))
 261
 262 /* APLL_LOCK */
 263 #define APLL_LOCK_VAL           (0x3E8)
 264 /* MPLL_LOCK */
 265 #define MPLL_LOCK_VAL           (0x2F1)
 266 /* CPLL_LOCK */
 267 #define CPLL_LOCK_VAL           (0x3E8)
 268 /* EPLL_LOCK */
 269 #define EPLL_LOCK_VAL           (0x2321)
 270 /* VPLL_LOCK */
 271 #define VPLL_LOCK_VAL           (0x2321)
 272 /* BPLL_LOCK */
 273 #define BPLL_LOCK_VAL           (0x3E8)
 274
 275 /* CLK_SRC_PERIC0 */
 276 /* SRC_CLOCK = SCLK_MPLL */
 277 #define PWM_SEL                 0
 278 #define UART4_SEL               6
 279 #define UART3_SEL               6
 280 #define UART2_SEL               6
 281 #define UART1_SEL               6
 282 #define UART0_SEL               6
 283 #define CLK_SRC_PERIC0_VAL      ((PWM_SEL << 24) \
 284                                 | (UART4_SEL << 16) \
 285                                 | (UART3_SEL << 12) \
 286                                 | (UART2_SEL << 8) \
 287                                 | (UART1_SEL << 4) \
 288                                 | (UART0_SEL << 0))
 289
 290 #define CLK_SRC_FSYS_VAL        0x66666
 291 #define CLK_DIV_FSYS0_VAL       0x0BB00000
 292 #define CLK_DIV_FSYS1_VAL       0x000f000f
 293 #define CLK_DIV_FSYS2_VAL       0x020f020f
 294 #define CLK_DIV_FSYS3_VAL       0x000f
 295
 296 /* CLK_DIV_PERIC0 */
 297 #define UART5_RATIO             8
 298 #define UART4_RATIO             8
 299 #define UART3_RATIO             8
 300 #define UART2_RATIO             8
 301 #define UART1_RATIO             8
 302 #define UART0_RATIO             8
 303 #define CLK_DIV_PERIC0_VAL      ((UART4_RATIO << 16) \
 304                                 | (UART3_RATIO << 12) \
 305                                 | (UART2_RATIO << 8) \
 306                                 | (UART1_RATIO << 4) \
 307                                 | (UART0_RATIO << 0))
 308
 309 /* CLK_DIV_PERIC3 */
 310 #define PWM_RATIO               8
 311 #define CLK_DIV_PERIC3_VAL      (PWM_RATIO << 0)
 312
 313 /* CLK_SRC_LEX */
 314 #define CLK_SRC_LEX_VAL         0x0
 315
 316 /* CLK_DIV_LEX */
 317 #define CLK_DIV_LEX_VAL         0x10
 318
 319 /* CLK_DIV_R0X */
 320 #define CLK_DIV_R0X_VAL         0x10
 321
 322 /* CLK_DIV_L0X */
 323 #define CLK_DIV_R1X_VAL         0x10
 324
 325 /* SCLK_SRC_ISP */
 326 #define SCLK_SRC_ISP_VAL        0x600
 327 /* CLK_DIV_ISP0 */
 328 #define CLK_DIV_ISP0_VAL        0x31
 329
 330 /* CLK_DIV_ISP1 */
 331 #define CLK_DIV_ISP1_VAL        0x0
 332
 333 /* CLK_DIV_ISP2 */
 334 #define CLK_DIV_ISP2_VAL        0x1
 335
 336 #define MPLL_DEC        (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
 337
 338 /*
 339  * TZPC Register Value :
 340  * R0SIZE: 0x0 : Size of secured ram
 341  */
 342 #define R0SIZE                  0x0
 343
 344 /*
 345  * TZPC Decode Protection Register Value :
 346  * DECPROTXSET: 0xFF : Set Decode region to non-secure
 347  */
 348 #define DECPROTXSET             0xFF
 349
 350 /* DMC Init */
 351 #define SET                     1
 352 #define RESET                   0
 353 /* (Memory Interleaving Size = 1 << IV_SIZE) */
 354 #define CONFIG_IV_SIZE          0x07
 355
 356 #define PHY_RESET_VAL   (0 << 0)
 357
 358 /*ZQ Configurations */
 359 #define PHY_CON16_RESET_VAL     0x08000304
 360
 361 #define ZQ_MODE_DDS_VAL         (0x5 << 24)
 362 #define ZQ_MODE_TERM_VAL        (0x5 << 21)
 363 #define SET_ZQ_MODE_DDS_VAL(x)  (x = (x & ~(0x7 << 24)) | ZQ_MODE_DDS_VAL)
 364 #define SET_ZQ_MODE_TERM_VAL(x) (x = (x & ~(0x7 << 21)) | ZQ_MODE_TERM_VAL)
 365
 366 #define ZQ_MODE_NOTERM          (1 << 19)
 367 #define ZQ_CLK_DIV_EN           (1 << 18)
 368 #define ZQ_MANUAL_STR           (1 << 1)
 369
 370 /* Channel and Chip Selection */
 371 #define CONFIG_DMC_CHANNELS             2
 372 #define CONFIG_CHIPS_PER_CHANNEL        2
 373
 374 #define SET_CMD_CHANNEL(x, y)   (x = (x & ~(1 << 28)) | y << 28)
 375 #define SET_CMD_CHIP(x, y)      (x = (x & ~(1 << 20)) | y << 20)
 376
 377 /* Diret Command */
 378 #define DIRECT_CMD_NOP          0x07000000
 379 #define DIRECT_CMD_MRS1         0x00071C00
 380 #define DIRECT_CMD_MRS2         0x00010BFC
 381 #define DIRECT_CMD_MRS3         0x00000708
 382 #define DIRECT_CMD_MRS4         0x00000818
 383 #define DIRECT_CMD_PALL         0x01000000
 384
 385 /* DLL Resync */
 386 #define FP_RSYNC                (1 << 3)
 387
 388 #define CONFIG_CTRL_DLL_ON(x, y)        (x = (x & ~(1 << 5)) | y << 5)
 389 #define CONFIG_CTRL_START(x, y)         (x = (x & ~(1 << 6)) | y << 6)
 390 #define SET_CTRL_FORCE_VAL(x, y)        (x = (x & ~(0x7F << 8)) | y << 8)
 391
 392 /* RDLVL */
 393 #define PHY_CON0_RESET_VAL      0x17023240
 394 #define DDR_MODE_LPDDR2         0x2
 395 #define BYTE_RDLVL_EN           (1 << 13)
 396 #define CTRL_ATGATE             (1 << 6)
 397 #define SET_CTRL_DDR_MODE(x, y) (x = (x & ~(0x3 << 11)) | y << 11)
 398
 399 #define PHY_CON1_RESET_VAL      0x9210100
 400 #define RDLVL_RDDATAPADJ        0x1
 401 #define SET_RDLVL_RDDATAPADJ    ((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\
 402                                         | RDLVL_RDDATAPADJ << 0)
 403
 404 #define PHY_CON2_RESET_VAL      0x00010004
 405 #define RDLVL_EN                (1 << 25)
 406 #define RDDSKEW_CLEAR           (1 << 13)
 407
 408 #define CTRL_RDLVL_DATA_EN      (1 << 1)
 409 #define LPDDR2_ADDR             0x00000208
 410
 411 #define DMC_MEMCONFIG0_VAL      0x00001323
 412 #define DMC_MEMCONFIG1_VAL      0x00001323
 413 #define DMC_MEMBASECONFIG0_VAL  0x00400780
 414 #define DMC_MEMBASECONFIG1_VAL  0x00800780
 415 #define DMC_MEMCONTROL_VAL      0x00212500
 416 #define DMC_PRECHCONFIG_VAL             0xFF000000
 417 #define DMC_PWRDNCONFIG_VAL             0xFFFF00FF
 418 #define DMC_TIMINGREF_VAL               0x0000005D
 419 #define DMC_TIMINGROW_VAL               0x2336544C
 420 #define DMC_TIMINGDATA_VAL              0x24202408
 421 #define DMC_TIMINGPOWER_VAL             0x38260235
 422
 423 #define CTRL_BSTLEN             0x04
 424 #define CTRL_RDLAT              0x08
 425 #define PHY_CON42_VAL           (CTRL_BSTLEN << 8 | CTRL_RDLAT << 0)
 426
 427 /* DQS, DQ, DEBUG offsets */
 428 #define SET_DQS_OFFSET_VAL      0x7F7F7F7F
 429 #define SET_DQ_OFFSET_VAL       0x7F7F7F7F
 430 #define SET_DEBUG_OFFSET_VAL    0x7F
 431
 432 #define RESET_DQS_OFFSET_VAL    0x08080808
 433 #define RESET_DQ_OFFSET_VAL     0x08080808
 434 #define RESET_DEBUG_OFFSET_VAL  0x8
 435
 436 #define CTRL_PULLD_DQ           (0x0F << 8)
 437 #define CTRL_PULLD_DQS          (0x0F << 0)
 438
 439 #define DFI_INIT_START          (1 << 28)
 440
 441 #define CLK_STOP_EN     (1 << 0)
 442 #define DPWRDN_EN       (1 << 1)
 443 #define DSREF_EN        (1 << 5)
 444
 445 #define AREF_EN                 (1 << 5)
 446 void sdelay(unsigned long);
 447 void mem_ctrl_init(void);
 448 void system_clock_init(void);
 449 void tzpc_init(void);
 450
 451 #endif