2 * Copyright (C) 2012 Samsung Electronics
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/dwmmc.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/mmc.h>
20 #include <asm/arch/pinmux.h>
21 #include <asm/arch/power.h>
22 #include <asm/arch/sromc.h>
23 #include <asm/arch/dp_info.h>
24 #include <power/pmic.h>
25 #include <power/max77686_pmic.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #ifdef CONFIG_SOUND_MAX98095
30 static void board_enable_audio_codec(void)
32 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
33 samsung_get_base_gpio_part1();
35 /* Enable MAX98095 Codec */
36 s5p_gpio_direction_output(&gpio1->x1, 7, 1);
37 s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
43 #ifdef CONFIG_SOUND_MAX98095
44 board_enable_audio_codec();
49 int board_eth_init(bd_t *bis)
52 u32 smc_bw_conf, smc_bc_conf;
53 struct fdt_sromc config;
56 /* Non-FDT configuration - bank number and timing parameters*/
57 config.bank = CONFIG_ENV_SROM_BANK;
60 config.timing[FDT_SROM_TACS] = 0x01;
61 config.timing[FDT_SROM_TCOS] = 0x01;
62 config.timing[FDT_SROM_TACC] = 0x06;
63 config.timing[FDT_SROM_TCOH] = 0x01;
64 config.timing[FDT_SROM_TAH] = 0x0C;
65 config.timing[FDT_SROM_TACP] = 0x09;
66 config.timing[FDT_SROM_PMC] = 0x01;
67 base_addr = CONFIG_SMC911X_BASE;
69 /* Ethernet needs data bus width of 16 bits */
70 if (config.width != 2) {
71 debug("%s: Unsupported bus width %d\n", __func__,
75 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
76 | SROMC_BYTE_ENABLE(config.bank);
78 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
79 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
80 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
81 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
82 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
83 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
84 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
86 /* Select and configure the SROMC bank */
87 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
88 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
89 return smc911x_initialize(0, base_addr);
94 #ifdef CONFIG_DISPLAY_BOARDINFO
97 printf("\nBoard: SMDK5250\n");
102 #ifdef CONFIG_GENERIC_MMC
103 int board_mmc_init(bd_t *bis)
105 int err, ret = 0, index, bus_width;
108 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
110 debug("SDMMC0 not configured\n");
113 /*EMMC: dwmmc Channel-0 with 8 bit bus width */
115 base = samsung_get_base_mmc() + (0x10000 * index);
117 err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
119 debug("dwmmc Channel-0 init failed\n");
122 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
124 debug("SDMMC2 not configured\n");
127 /*SD: dwmmc Channel-2 with 4 bit bus width */
129 base = samsung_get_base_mmc() + (0x10000 * index);
131 err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
133 debug("dwmmc Channel-2 init failed\n");
140 void board_i2c_init(const void *blob)
144 for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
145 exynos_pinmux_config((PERIPH_ID_I2C0 + i),
150 #if defined(CONFIG_POWER)
151 #ifdef CONFIG_POWER_MAX77686
152 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
157 ret = pmic_reg_read(p, reg, &val);
159 debug("%s: PMIC %d register read failed\n", __func__, reg);
163 ret = pmic_reg_write(p, reg, val);
165 debug("%s: PMIC %d register write failed\n", __func__, reg);
171 static int max77686_init(void)
175 if (pmic_init(I2C_PMIC))
178 p = pmic_get("MAX77686_PMIC");
185 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
188 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
189 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
193 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
194 MAX77686_BUCK1OUT_1V)) {
195 debug("%s: PMIC %d register write failed\n", __func__,
196 MAX77686_REG_PMIC_BUCK1OUT);
200 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
201 MAX77686_BUCK1CTRL_EN))
205 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
206 MAX77686_BUCK2DVS1_1_3V)) {
207 debug("%s: PMIC %d register write failed\n", __func__,
208 MAX77686_REG_PMIC_BUCK2DVS1);
212 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
213 MAX77686_BUCK2CTRL_ON))
217 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
218 MAX77686_BUCK3DVS1_1_0125V)) {
219 debug("%s: PMIC %d register write failed\n", __func__,
220 MAX77686_REG_PMIC_BUCK3DVS1);
224 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
225 MAX77686_BUCK3CTRL_ON))
229 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
230 MAX77686_BUCK4DVS1_1_2V)) {
231 debug("%s: PMIC %d register write failed\n", __func__,
232 MAX77686_REG_PMIC_BUCK4DVS1);
236 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
237 MAX77686_BUCK3CTRL_ON))
241 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
242 MAX77686_LD02CTRL1_1_5V | EN_LDO))
246 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
247 MAX77686_LD03CTRL1_1_8V | EN_LDO))
251 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
252 MAX77686_LD05CTRL1_1_8V | EN_LDO))
256 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
257 MAX77686_LD10CTRL1_1_8V | EN_LDO))
262 #endif /* CONFIG_POWER_MAX77686 */
264 int exynos_power_init(void)
268 #ifdef CONFIG_POWER_MAX77686
269 ret = max77686_init();
273 #endif /* CONFIG_POWER */
276 void exynos_cfg_lcd_gpio(void)
278 struct exynos5_gpio_part1 *gpio1 =
279 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
282 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
283 s5p_gpio_set_value(&gpio1->b2, 0, 1);
286 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
287 s5p_gpio_set_value(&gpio1->x1, 5, 1);
289 /* Set Hotplug detect for DP */
290 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
293 void exynos_set_dp_phy(unsigned int onoff)
295 set_dp_phy_ctrl(onoff);
298 vidinfo_t panel_info = {
304 .vl_clkp = CONFIG_SYS_LOW,
305 .vl_hsp = CONFIG_SYS_LOW,
306 .vl_vsp = CONFIG_SYS_LOW,
307 .vl_dp = CONFIG_SYS_LOW,
308 .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
310 /* wDP panel timing infomation */
318 .vl_cmd_allow_len = 0xf,
321 .dual_lcd_enabled = 0,
326 .interface_mode = FIMD_RGB_INTERFACE,
330 static struct edp_device_info edp_info = {
343 .lt_status = DP_LT_NONE,
347 .bist_mode = DP_DISABLE,
348 .bist_pattern = NO_PATTERN,
349 .h_sync_polarity = 0,
350 .v_sync_polarity = 0,
352 .color_space = COLOR_RGB,
353 .dynamic_range = VESA,
354 .ycbcr_coeff = COLOR_YCBCR601,
355 .color_depth = COLOR_8,
359 static struct exynos_dp_platform_data dp_platform_data = {
360 .edp_dev_info = &edp_info,
363 void init_panel_info(vidinfo_t *vid)
365 vid->rgb_mode = MODE_RGB_P;
366 exynos_set_dp_platform_data(&dp_platform_data);