2 * Copyright (C) 2012 Samsung Electronics
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/mmc.h>
33 #include <asm/arch/pinmux.h>
34 #include <asm/arch/power.h>
35 #include <asm/arch/sromc.h>
36 #include <asm/arch/dp_info.h>
37 #include <power/pmic.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #ifdef CONFIG_USB_EHCI_EXYNOS
42 int board_usb_vbus_init(void)
44 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
45 samsung_get_base_gpio_part1();
47 /* Enable VBUS power switch */
48 s5p_gpio_direction_output(&gpio1->x2, 6, 1);
50 /* VBUS turn ON time */
59 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
60 #ifdef CONFIG_EXYNOS_SPI
63 #ifdef CONFIG_USB_EHCI_EXYNOS
64 board_usb_vbus_init();
71 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
72 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
73 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
74 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
75 + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
76 + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
77 + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
78 + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
82 #if defined(CONFIG_POWER)
83 int power_init_board(void)
85 if (pmic_init(I2C_PMIC))
92 void dram_init_banksize(void)
94 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
95 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
97 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
98 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
100 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
101 gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
103 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
104 gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
106 gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
107 gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
109 gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
110 gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
112 gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
113 gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
115 gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
116 gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
120 #ifdef CONFIG_OF_CONTROL
121 static int decode_sromc(const void *blob, struct fdt_sromc *config)
126 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
128 debug("Could not find SROMC node\n");
132 config->bank = fdtdec_get_int(blob, node, "bank", 0);
133 config->width = fdtdec_get_int(blob, node, "width", 2);
135 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
136 FDT_SROM_TIMING_COUNT);
138 debug("Could not decode SROMC configuration\n");
139 return -FDT_ERR_NOTFOUND;
146 int board_eth_init(bd_t *bis)
148 #ifdef CONFIG_SMC911X
149 u32 smc_bw_conf, smc_bc_conf;
150 struct fdt_sromc config;
151 fdt_addr_t base_addr;
154 #ifdef CONFIG_OF_CONTROL
155 node = decode_sromc(gd->fdt_blob, &config);
157 debug("%s: Could not find sromc configuration\n", __func__);
160 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
162 debug("%s: Could not find lan9215 configuration\n", __func__);
166 /* We now have a node, so any problems from now on are errors */
167 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
168 if (base_addr == FDT_ADDR_T_NONE) {
169 debug("%s: Could not find lan9215 address\n", __func__);
173 /* Non-FDT configuration - bank number and timing parameters*/
174 config.bank = CONFIG_ENV_SROM_BANK;
177 config.timing[FDT_SROM_TACS] = 0x01;
178 config.timing[FDT_SROM_TCOS] = 0x01;
179 config.timing[FDT_SROM_TACC] = 0x06;
180 config.timing[FDT_SROM_TCOH] = 0x01;
181 config.timing[FDT_SROM_TAH] = 0x0C;
182 config.timing[FDT_SROM_TACP] = 0x09;
183 config.timing[FDT_SROM_PMC] = 0x01;
184 base_addr = CONFIG_SMC911X_BASE;
187 /* Ethernet needs data bus width of 16 bits */
188 if (config.width != 2) {
189 debug("%s: Unsupported bus width %d\n", __func__,
193 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
194 | SROMC_BYTE_ENABLE(config.bank);
196 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
197 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
198 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
199 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
200 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
201 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
202 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
204 /* Select and configure the SROMC bank */
205 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
206 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
207 return smc911x_initialize(0, base_addr);
212 #ifdef CONFIG_DISPLAY_BOARDINFO
215 printf("\nBoard: SMDK5250\n");
221 #ifdef CONFIG_GENERIC_MMC
222 int board_mmc_init(bd_t *bis)
226 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
228 debug("SDMMC0 not configured\n");
232 err = s5p_mmc_init(0, 8);
237 static int board_uart_init(void)
241 err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
243 debug("UART0 not configured\n");
247 err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
249 debug("UART1 not configured\n");
253 err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
255 debug("UART2 not configured\n");
259 err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
261 debug("UART3 not configured\n");
268 #ifdef CONFIG_BOARD_EARLY_INIT_F
269 int board_early_init_f(void)
272 err = board_uart_init();
274 debug("UART init failed\n");
277 #ifdef CONFIG_SYS_I2C_INIT_BOARD
278 board_i2c_init(gd->fdt_blob);
285 void cfg_lcd_gpio(void)
287 struct exynos5_gpio_part1 *gpio1 =
288 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
291 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
292 s5p_gpio_set_value(&gpio1->b2, 0, 1);
295 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
296 s5p_gpio_set_value(&gpio1->x1, 5, 1);
298 /* Set Hotplug detect for DP */
299 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
302 vidinfo_t panel_info = {
308 .vl_clkp = CONFIG_SYS_LOW,
309 .vl_hsp = CONFIG_SYS_LOW,
310 .vl_vsp = CONFIG_SYS_LOW,
311 .vl_dp = CONFIG_SYS_LOW,
312 .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
314 /* wDP panel timing infomation */
322 .vl_cmd_allow_len = 0xf,
325 .cfg_gpio = cfg_lcd_gpio,
326 .backlight_on = NULL,
327 .lcd_power_on = NULL,
329 .dual_lcd_enabled = 0,
334 .interface_mode = FIMD_RGB_INTERFACE,
338 static struct edp_device_info edp_info = {
351 .lt_status = DP_LT_NONE,
355 .bist_mode = DP_DISABLE,
356 .bist_pattern = NO_PATTERN,
357 .h_sync_polarity = 0,
358 .v_sync_polarity = 0,
360 .color_space = COLOR_RGB,
361 .dynamic_range = VESA,
362 .ycbcr_coeff = COLOR_YCBCR601,
363 .color_depth = COLOR_8,
367 static struct exynos_dp_platform_data dp_platform_data = {
368 .phy_enable = set_dp_phy_ctrl,
369 .edp_dev_info = &edp_info,
372 void init_panel_info(vidinfo_t *vid)
374 vid->rgb_mode = MODE_RGB_P,
376 exynos_set_dp_platform_data(&dp_platform_data);