2 * Copyright (C) 2012 Samsung Electronics
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/mmc.h>
34 #include <asm/arch/pinmux.h>
35 #include <asm/arch/power.h>
36 #include <asm/arch/sromc.h>
37 #include <asm/arch/dp_info.h>
38 #include <power/pmic.h>
39 #include <power/max77686_pmic.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 #if defined CONFIG_EXYNOS_TMU
46 * Boot Time Thermal Analysis for SoC temperature threshold breach
48 static void boot_temp_check(void)
52 switch (tmu_monitor(&temp)) {
53 /* Status TRIPPED ans WARNING means corresponding threshold breach */
54 case TMU_STATUS_TRIPPED:
55 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
59 case TMU_STATUS_WARNING:
60 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
63 * TMU_STATUS_INIT means something is wrong with temperature sensing
64 * and TMU status was changed back from NORMAL to INIT.
68 debug("EXYNOS_TMU: Unknown TMU state\n");
73 #ifdef CONFIG_USB_EHCI_EXYNOS
74 int board_usb_vbus_init(void)
76 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
77 samsung_get_base_gpio_part1();
79 /* Enable VBUS power switch */
80 s5p_gpio_direction_output(&gpio1->x2, 6, 1);
82 /* VBUS turn ON time */
89 #ifdef CONFIG_SOUND_MAX98095
90 static void board_enable_audio_codec(void)
92 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
93 samsung_get_base_gpio_part1();
95 /* Enable MAX98095 Codec */
96 s5p_gpio_direction_output(&gpio1->x1, 7, 1);
97 s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
103 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
105 #if defined CONFIG_EXYNOS_TMU
106 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
107 debug("%s: Failed to init TMU\n", __func__);
113 #ifdef CONFIG_EXYNOS_SPI
116 #ifdef CONFIG_USB_EHCI_EXYNOS
117 board_usb_vbus_init();
119 #ifdef CONFIG_SOUND_MAX98095
120 board_enable_audio_codec();
127 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
128 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
129 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
130 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
131 + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
132 + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
133 + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
134 + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
138 #if defined(CONFIG_POWER)
139 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
144 ret = pmic_reg_read(p, reg, &val);
146 debug("%s: PMIC %d register read failed\n", __func__, reg);
150 ret = pmic_reg_write(p, reg, val);
152 debug("%s: PMIC %d register write failed\n", __func__, reg);
158 int power_init_board(void)
164 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
166 if (pmic_init(I2C_PMIC))
169 p = pmic_get("MAX77686_PMIC");
176 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
179 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
180 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
184 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
185 MAX77686_BUCK1OUT_1V)) {
186 debug("%s: PMIC %d register write failed\n", __func__,
187 MAX77686_REG_PMIC_BUCK1OUT);
191 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
192 MAX77686_BUCK1CTRL_EN))
196 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
197 MAX77686_BUCK2DVS1_1_3V)) {
198 debug("%s: PMIC %d register write failed\n", __func__,
199 MAX77686_REG_PMIC_BUCK2DVS1);
203 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
204 MAX77686_BUCK2CTRL_ON))
208 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
209 MAX77686_BUCK3DVS1_1_0125V)) {
210 debug("%s: PMIC %d register write failed\n", __func__,
211 MAX77686_REG_PMIC_BUCK3DVS1);
215 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
216 MAX77686_BUCK3CTRL_ON))
220 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
221 MAX77686_BUCK4DVS1_1_2V)) {
222 debug("%s: PMIC %d register write failed\n", __func__,
223 MAX77686_REG_PMIC_BUCK4DVS1);
227 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
228 MAX77686_BUCK3CTRL_ON))
232 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
233 MAX77686_LD02CTRL1_1_5V | EN_LDO))
237 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
238 MAX77686_LD03CTRL1_1_8V | EN_LDO))
242 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
243 MAX77686_LD05CTRL1_1_8V | EN_LDO))
247 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
248 MAX77686_LD10CTRL1_1_8V | EN_LDO))
255 void dram_init_banksize(void)
257 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
258 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
260 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
261 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
263 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
264 gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
266 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
267 gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
269 gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
270 gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
272 gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
273 gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
275 gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
276 gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
278 gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
279 gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
283 #ifdef CONFIG_OF_CONTROL
284 static int decode_sromc(const void *blob, struct fdt_sromc *config)
289 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
291 debug("Could not find SROMC node\n");
295 config->bank = fdtdec_get_int(blob, node, "bank", 0);
296 config->width = fdtdec_get_int(blob, node, "width", 2);
298 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
299 FDT_SROM_TIMING_COUNT);
301 debug("Could not decode SROMC configuration\n");
302 return -FDT_ERR_NOTFOUND;
309 int board_eth_init(bd_t *bis)
311 #ifdef CONFIG_SMC911X
312 u32 smc_bw_conf, smc_bc_conf;
313 struct fdt_sromc config;
314 fdt_addr_t base_addr;
317 #ifdef CONFIG_OF_CONTROL
318 node = decode_sromc(gd->fdt_blob, &config);
320 debug("%s: Could not find sromc configuration\n", __func__);
323 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
325 debug("%s: Could not find lan9215 configuration\n", __func__);
329 /* We now have a node, so any problems from now on are errors */
330 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
331 if (base_addr == FDT_ADDR_T_NONE) {
332 debug("%s: Could not find lan9215 address\n", __func__);
336 /* Non-FDT configuration - bank number and timing parameters*/
337 config.bank = CONFIG_ENV_SROM_BANK;
340 config.timing[FDT_SROM_TACS] = 0x01;
341 config.timing[FDT_SROM_TCOS] = 0x01;
342 config.timing[FDT_SROM_TACC] = 0x06;
343 config.timing[FDT_SROM_TCOH] = 0x01;
344 config.timing[FDT_SROM_TAH] = 0x0C;
345 config.timing[FDT_SROM_TACP] = 0x09;
346 config.timing[FDT_SROM_PMC] = 0x01;
347 base_addr = CONFIG_SMC911X_BASE;
350 /* Ethernet needs data bus width of 16 bits */
351 if (config.width != 2) {
352 debug("%s: Unsupported bus width %d\n", __func__,
356 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
357 | SROMC_BYTE_ENABLE(config.bank);
359 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
360 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
361 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
362 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
363 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
364 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
365 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
367 /* Select and configure the SROMC bank */
368 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
369 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
370 return smc911x_initialize(0, base_addr);
375 #ifdef CONFIG_DISPLAY_BOARDINFO
378 #ifdef CONFIG_OF_CONTROL
379 const char *board_name;
381 board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
382 if (board_name == NULL)
383 printf("\nUnknown Board\n");
385 printf("\nBoard: %s\n", board_name);
387 printf("\nBoard: SMDK5250\n");
393 #ifdef CONFIG_GENERIC_MMC
394 int board_mmc_init(bd_t *bis)
398 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
400 debug("SDMMC0 not configured\n");
404 err = s5p_mmc_init(0, 8);
409 static int board_uart_init(void)
413 err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
415 debug("UART0 not configured\n");
419 err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
421 debug("UART1 not configured\n");
425 err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
427 debug("UART2 not configured\n");
431 err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
433 debug("UART3 not configured\n");
440 #ifdef CONFIG_BOARD_EARLY_INIT_F
441 int board_early_init_f(void)
444 err = board_uart_init();
446 debug("UART init failed\n");
449 #ifdef CONFIG_SYS_I2C_INIT_BOARD
450 board_i2c_init(gd->fdt_blob);
457 void exynos_cfg_lcd_gpio(void)
459 struct exynos5_gpio_part1 *gpio1 =
460 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
463 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
464 s5p_gpio_set_value(&gpio1->b2, 0, 1);
467 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
468 s5p_gpio_set_value(&gpio1->x1, 5, 1);
470 /* Set Hotplug detect for DP */
471 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
474 vidinfo_t panel_info = {
480 .vl_clkp = CONFIG_SYS_LOW,
481 .vl_hsp = CONFIG_SYS_LOW,
482 .vl_vsp = CONFIG_SYS_LOW,
483 .vl_dp = CONFIG_SYS_LOW,
484 .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
486 /* wDP panel timing infomation */
494 .vl_cmd_allow_len = 0xf,
497 .dual_lcd_enabled = 0,
502 .interface_mode = FIMD_RGB_INTERFACE,
506 void exynos_set_dp_phy(unsigned int onoff)
508 set_dp_phy_ctrl(onoff);
511 static struct edp_device_info edp_info = {
524 .lt_status = DP_LT_NONE,
528 .bist_mode = DP_DISABLE,
529 .bist_pattern = NO_PATTERN,
530 .h_sync_polarity = 0,
531 .v_sync_polarity = 0,
533 .color_space = COLOR_RGB,
534 .dynamic_range = VESA,
535 .ycbcr_coeff = COLOR_YCBCR601,
536 .color_depth = COLOR_8,
540 static struct exynos_dp_platform_data dp_platform_data = {
541 .edp_dev_info = &edp_info,
544 void init_panel_info(vidinfo_t *vid)
546 vid->rgb_mode = MODE_RGB_P,
548 exynos_set_dp_platform_data(&dp_platform_data);