2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the Samsung SMDK2410 by
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
12 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/s3c6400.h>
40 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
41 #elif defined(CONFIG_SERIAL2)
42 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
44 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
48 .word CONFIG_SYS_TEXT_BASE
55 ldr r0, =ELFIN_GPIO_BASE
57 str r1, [r0, #GPNCON_OFFSET]
60 str r1, [r0, #GPNPUD_OFFSET]
63 str r1, [r0, #GPNDAT_OFFSET]
65 /* Disable Watchdog */
66 ldr r0, =0x7e000000 @0x7e004000
71 /* External interrupt pending clear */
72 ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
76 ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
77 ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
79 /* Disable all interrupts (VIC0 and VIC1) */
81 str r3, [r0, #oINTMSK]
82 str r3, [r1, #oINTMSK]
84 /* Set all interrupts as IRQ */
86 str r3, [r0, #oINTMOD]
87 str r3, [r1, #oINTMOD]
89 /* Pending Interrupt Clear */
91 str r3, [r0, #oVECTADDR]
92 str r3, [r1, #oVECTADDR]
94 /* init system clock */
97 #ifndef CONFIG_NAND_SPL
102 #ifdef CONFIG_BOOT_NAND
103 /* simple init for NAND */
107 /* Memory subsystem address 0x7e00f120 */
108 ldr r0, =ELFIN_MEM_SYS_CFG
110 /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
111 mov r1, #S3C64XX_MEM_SYS_CFG_NAND
116 /* Wakeup support. Don't know if it's going to be used, untested. */
117 ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
119 bic r1, r1, #0xfffffff7
129 /* Clear wakeup status register */
130 ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
135 ldr r0, =ELFIN_GPIO_BASE
137 str r1, [r0, #GPNDAT_OFFSET]
139 /* Load return address and jump to kernel */
140 ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
141 /* r1 = physical address of s3c6400_cpu_resume function */
143 /* Jump to kernel (sleep-s3c6400.S) */
148 * system_clock_init: Initialize core clock and bus clock.
149 * void system_clock_init(void)
152 ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
154 #ifdef CONFIG_SYNC_MODE
155 ldr r1, [r0, #OTHERS_OFFSET]
158 str r1, [r0, #OTHERS_OFFSET]
168 str r1, [r0, #OTHERS_OFFSET]
171 ldr r1, [r0, #OTHERS_OFFSET]
176 #else /* ASYNC Mode */
184 * This was unconditional in original Samsung sources, but it doesn't
185 * seem to make much sense on S3C6400.
187 #ifndef CONFIG_S3C6400
188 ldr r1, [r0, #OTHERS_OFFSET]
191 str r1, [r0, #OTHERS_OFFSET]
194 ldr r1, [r0, #OTHERS_OFFSET]
200 ldr r1, [r0, #OTHERS_OFFSET]
202 str r1, [r0, #OTHERS_OFFSET]
207 str r1, [r0, #APLL_LOCK_OFFSET]
208 str r1, [r0, #MPLL_LOCK_OFFSET]
210 /* Set Clock Divider */
211 ldr r1, [r0, #CLK_DIV0_OFFSET]
217 str r1, [r0, #CLK_DIV0_OFFSET]
220 str r1, [r0, #APLL_CON_OFFSET]
222 str r1, [r0, #MPLL_CON_OFFSET]
224 /* FOUT of EPLL is 96MHz */
226 str r1, [r0, #EPLL_CON0_OFFSET]
228 str r1, [r0, #EPLL_CON1_OFFSET]
230 /* APLL, MPLL, EPLL select to Fout */
231 ldr r1, [r0, #CLK_SRC_OFFSET]
233 str r1, [r0, #CLK_SRC_OFFSET]
235 /* wait at least 200us to stablize all clock */
240 /* Synchronization for VIC port */
241 #if defined(CONFIG_SYNC_MODE)
242 ldr r1, [r0, #OTHERS_OFFSET]
244 str r1, [r0, #OTHERS_OFFSET]
245 #elif !defined(CONFIG_S3C6400)
246 /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
247 ldr r1, [r0, #OTHERS_OFFSET]
249 str r1, [r0, #OTHERS_OFFSET]
254 #ifndef CONFIG_NAND_SPL
256 * uart_asm_init: Initialize UART's pins
259 /* set GPIO to enable UART */
260 ldr r0, =ELFIN_GPIO_BASE
262 str r1, [r0, #GPACON_OFFSET]
266 #ifdef CONFIG_BOOT_NAND
268 * NAND Interface init for SMDK6400
271 ldr r0, =ELFIN_NAND_BASE
272 ldr r1, [r0, #NFCONF_OFFSET]
275 str r1, [r0, #NFCONF_OFFSET]
277 ldr r1, [r0, #NFCONT_OFFSET]
279 str r1, [r0, #NFCONT_OFFSET]
284 #ifdef CONFIG_ENABLE_MMU
286 * MMU Table for SMDK6400
289 /* form a first-level section entry */
290 .macro FL_SECTION_ENTRY base,ap,d,c,b
291 .word (\base << 20) | (\ap << 10) | \
292 (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
295 .section .mmudata, "a"
297 /* the following alignment creates the mmu table at address 0x4000. */
301 /* 1:1 mapping for debugging */
303 FL_SECTION_ENTRY __base, 3, 0, 0, 0
304 .set __base, __base + 1
307 /* access is not allowed. */
312 /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
315 FL_SECTION_ENTRY __base, 3, 0, 1, 1
316 .set __base, __base + 1
319 /* access is not allowed. */