2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/power.h>
24 /* r5 has always zero */
27 ldr r8, =S5PC100_GPIO_BASE
29 /* Disable Watchdog */
30 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
35 ldr r0, =S5PC100_SROMC_BASE
39 /* S5PC100 has 3 groups of interrupt sources */
40 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
41 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
42 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
44 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
46 str r3, [r0, #0x14] @INTENCLEAR
47 str r3, [r1, #0x14] @INTENCLEAR
48 str r3, [r2, #0x14] @INTENCLEAR
50 /* Set all interrupts as IRQ */
51 str r5, [r0, #0xc] @INTSELECT
52 str r5, [r1, #0xc] @INTSELECT
53 str r5, [r2, #0xc] @INTSELECT
55 /* Pending Interrupt Clear */
56 str r5, [r0, #0xf00] @INTADDRESS
57 str r5, [r1, #0xf00] @INTADDRESS
58 str r5, [r2, #0xf00] @INTADDRESS
71 * system_clock_init: Initialize core clock and bus clock.
72 * void system_clock_init(void)
75 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
77 /* Set Clock divider */
86 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
87 str r1, [r8, #0x000] @ APLL_LOCK
88 str r1, [r8, #0x004] @ MPLL_LOCK
89 str r1, [r8, #0x008] @ EPLL_LOCK
90 str r1, [r8, #0x00C] @ HPLL_LOCK
93 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
96 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
99 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
105 /* Set Source Clock */
106 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
107 str r1, [r8, #0x200] @ CLK_SRC0
109 ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
110 str r1, [r8, #0x204] @ CLK_SRC1
112 ldr r1, =0x9000 @ ARMCLK/4
113 str r1, [r8, #0x400] @ CLK_OUT
115 /* wait at least 200us to stablize all clock */
123 * uart_asm_init: Initialize UART's pins
128 str r1, [r0, #0x0] @ GPA0_CON
130 str r1, [r0, #0x20] @ GPA1_CON
135 * tzpc_asm_init: Initialize TZPC