2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/power.h>
23 /* r5 has always zero */
26 ldr r8, =S5PC100_GPIO_BASE
28 /* Disable Watchdog */
29 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
34 ldr r0, =S5PC100_SROMC_BASE
38 /* S5PC100 has 3 groups of interrupt sources */
39 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
40 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
41 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
43 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
45 str r3, [r0, #0x14] @INTENCLEAR
46 str r3, [r1, #0x14] @INTENCLEAR
47 str r3, [r2, #0x14] @INTENCLEAR
49 /* Set all interrupts as IRQ */
50 str r5, [r0, #0xc] @INTSELECT
51 str r5, [r1, #0xc] @INTSELECT
52 str r5, [r2, #0xc] @INTSELECT
54 /* Pending Interrupt Clear */
55 str r5, [r0, #0xf00] @INTADDRESS
56 str r5, [r1, #0xf00] @INTADDRESS
57 str r5, [r2, #0xf00] @INTADDRESS
70 * system_clock_init: Initialize core clock and bus clock.
71 * void system_clock_init(void)
74 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
76 /* Set Clock divider */
85 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
86 str r1, [r8, #0x000] @ APLL_LOCK
87 str r1, [r8, #0x004] @ MPLL_LOCK
88 str r1, [r8, #0x008] @ EPLL_LOCK
89 str r1, [r8, #0x00C] @ HPLL_LOCK
92 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
95 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
98 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
104 /* Set Source Clock */
105 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
106 str r1, [r8, #0x200] @ CLK_SRC0
108 ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
109 str r1, [r8, #0x204] @ CLK_SRC1
111 ldr r1, =0x9000 @ ARMCLK/4
112 str r1, [r8, #0x400] @ CLK_OUT
114 /* wait at least 200us to stablize all clock */
122 * uart_asm_init: Initialize UART's pins
127 str r1, [r0, #0x0] @ GPA0_CON
129 str r1, [r0, #0x20] @ GPA1_CON
134 * tzpc_asm_init: Initialize TZPC