2 * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
4 * Copyright (C) 2009 Samsung Electrnoics
5 * Inki Dae <inki.dae@samsung.com>
6 * Heungjun Kim <riverful.kim@samsung.com>
7 * Minkyu Kang <mk7.kang@samsung.com>
8 * Kyungmin Park <kyungmin.park@samsung.com>
10 * SPDX-License-Identifier: GPL-2.0+
15 .globl mem_ctrl_asm_init
17 ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
19 /* DLL parameter setting */
21 str r1, [r6, #0x018] @ PHYCONTROL0
23 str r1, [r6, #0x01C] @ PHYCONTROL1
25 str r1, [r6, #0x020] @ PHYCONTROL2
29 str r1, [r6, #0x018] @ PHYCONTROL0
33 str r1, [r6, #0x018] @ PHYCONTROL0
35 /* Force value locking for DLL off */
36 str r1, [r6, #0x018] @ PHYCONTROL0
40 str r1, [r6, #0x018] @ PHYCONTROL0
42 /* auto refresh off */
44 str r1, [r6, #0x000] @ CONCONTROL
47 * Burst Length 4, 2 chips, 32-bit, LPDDR
48 * OFF: dynamic self refresh, force precharge, dynamic power down off
51 str r1, [r6, #0x004] @ MEMCONTROL
55 * If Bank0 has OneDRAM we place it at 0x2800'0000
56 * So finally Bank1 should address start at at 0x2000'0000
71 /* if r4 is 1, swap the bank */
73 orreq r1, r1, #0x08000000
74 str r1, [r6, #0x008] @ MEMCONFIG0
86 /* if r4 is 1, swap the bank */
88 biceq r1, r1, #0x08000000
89 str r1, [r6, #0x00c] @ MEMCONFIG1
92 str r1, [r6, #0x014] @ PRECHCONFIG
95 * FIXME: Please verify these values
96 * 7.8us * 166MHz %LE %LONG1294(0x50E)
97 * 7.8us * 133MHz %LE %LONG1038(0x40E),
98 * 7.8us * 100MHz %LE %LONG780(0x30C),
99 * 7.8us * 20MHz %LE %LONG156(0x9C),
100 * 7.8us * 10MHz %LE %LONG78(0x4E)
103 str r1, [r6, #0x030] @ TIMINGAREF
107 str r1, [r6, #0x034] @ TIMINGROW
109 /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
111 str r1, [r6, #0x038] @ TIMINGDATA
113 /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
115 str r1, [r6, #0x03C] @ TIMINGPOWER
119 str r1, [r6, #0x010] @ DIRECTCMD
123 str r1, [r6, #0x010] @ DIRECTCMD
127 str r1, [r6, #0x010] @ DIRECTCMD
129 str r1, [r6, #0x010] @ DIRECTCMD
131 /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
133 str r1, [r6, #0x010] @ DIRECTCMD
137 str r1, [r6, #0x010] @ DIRECTCMD
141 str r1, [r6, #0x010] @ DIRECTCMD
145 str r1, [r6, #0x010] @ DIRECTCMD
147 str r1, [r6, #0x010] @ DIRECTCMD
149 /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
151 str r1, [r6, #0x010] @ DIRECTCMD
153 /* auto refresh on */
155 str r1, [r6, #0x000] @ CONCONTROL
159 str r1, [r6, #0x028] @ PWRDNCONFIG
163 str r1, [r6, #0x004] @ MEMCONTROL
166 /* Try to test memory area */
173 str r4, [r1, #0x4] @ dummy write