2 * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
4 * Copyright (C) 2009 Samsung Electrnoics
5 * Inki Dae <inki.dae@samsung.com>
6 * Heungjun Kim <riverful.kim@samsung.com>
7 * Minkyu Kang <mk7.kang@samsung.com>
8 * Kyungmin Park <kyungmin.park@samsung.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 .globl mem_ctrl_asm_init
33 ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
35 /* DLL parameter setting */
37 str r1, [r6, #0x018] @ PHYCONTROL0
39 str r1, [r6, #0x01C] @ PHYCONTROL1
41 str r1, [r6, #0x020] @ PHYCONTROL2
45 str r1, [r6, #0x018] @ PHYCONTROL0
49 str r1, [r6, #0x018] @ PHYCONTROL0
51 /* Force value locking for DLL off */
52 str r1, [r6, #0x018] @ PHYCONTROL0
56 str r1, [r6, #0x018] @ PHYCONTROL0
58 /* auto refresh off */
60 str r1, [r6, #0x000] @ CONCONTROL
63 * Burst Length 4, 2 chips, 32-bit, LPDDR
64 * OFF: dynamic self refresh, force precharge, dynamic power down off
67 str r1, [r6, #0x004] @ MEMCONTROL
71 * If Bank0 has OneDRAM we place it at 0x2800'0000
72 * So finally Bank1 should address start at at 0x2000'0000
87 /* if r4 is 1, swap the bank */
89 orreq r1, r1, #0x08000000
90 str r1, [r6, #0x008] @ MEMCONFIG0
102 /* if r4 is 1, swap the bank */
104 biceq r1, r1, #0x08000000
105 str r1, [r6, #0x00c] @ MEMCONFIG1
108 str r1, [r6, #0x014] @ PRECHCONFIG
111 * FIXME: Please verify these values
112 * 7.8us * 166MHz %LE %LONG1294(0x50E)
113 * 7.8us * 133MHz %LE %LONG1038(0x40E),
114 * 7.8us * 100MHz %LE %LONG780(0x30C),
115 * 7.8us * 20MHz %LE %LONG156(0x9C),
116 * 7.8us * 10MHz %LE %LONG78(0x4E)
119 str r1, [r6, #0x030] @ TIMINGAREF
123 str r1, [r6, #0x034] @ TIMINGROW
125 /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
127 str r1, [r6, #0x038] @ TIMINGDATA
129 /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
131 str r1, [r6, #0x03C] @ TIMINGPOWER
135 str r1, [r6, #0x010] @ DIRECTCMD
139 str r1, [r6, #0x010] @ DIRECTCMD
143 str r1, [r6, #0x010] @ DIRECTCMD
145 str r1, [r6, #0x010] @ DIRECTCMD
147 /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
149 str r1, [r6, #0x010] @ DIRECTCMD
153 str r1, [r6, #0x010] @ DIRECTCMD
157 str r1, [r6, #0x010] @ DIRECTCMD
161 str r1, [r6, #0x010] @ DIRECTCMD
163 str r1, [r6, #0x010] @ DIRECTCMD
165 /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
167 str r1, [r6, #0x010] @ DIRECTCMD
169 /* auto refresh on */
171 str r1, [r6, #0x000] @ CONCONTROL
175 str r1, [r6, #0x028] @ PWRDNCONFIG
179 str r1, [r6, #0x004] @ MEMCONTROL
182 /* Try to test memory area */
189 str r4, [r1, #0x4] @ dummy write