2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/mmc.h>
32 #include <asm/arch/pinmux.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/clk.h>
35 #include <asm/arch/mipi_dsim.h>
36 #include <asm/arch/watchdog.h>
37 #include <asm/arch/power.h>
38 #include <power/pmic.h>
39 #include <usb/s3c_udc.h>
40 #include <power/max8997_pmic.h>
42 #include <power/max8997_muic.h>
43 #include <power/battery.h>
44 #include <power/max17042_fg.h>
45 #include <usb_mass_storage.h>
49 DECLARE_GLOBAL_DATA_PTR;
51 unsigned int board_rev;
53 #ifdef CONFIG_REVISION_TAG
54 u32 get_board_rev(void)
60 static void check_hw_revision(void);
62 static int hwrevision(int rev)
64 return (board_rev & 0xf) == rev;
67 struct s3c_plat_otg_data s5pc210_otg_data;
71 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
74 printf("HW Revision:\t0x%x\n", board_rev);
79 void i2c_init_board(void)
81 struct exynos4_gpio_part1 *gpio1 =
82 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
83 struct exynos4_gpio_part2 *gpio2 =
84 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
87 s5p_gpio_direction_output(&gpio1->b, 7, 1);
88 s5p_gpio_direction_output(&gpio1->b, 6, 1);
90 s5p_gpio_direction_output(&gpio2->y4, 0, 1);
91 s5p_gpio_direction_output(&gpio2->y4, 1, 1);
94 static void trats_low_power_mode(void)
96 struct exynos4_clock *clk =
97 (struct exynos4_clock *)samsung_get_base_clock();
98 struct exynos4_power *pwr =
99 (struct exynos4_power *)samsung_get_base_power();
101 /* Power down CORE1 */
102 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
103 writel(0x0, &pwr->arm_core1_configuration);
105 /* Change the APLL frequency */
106 /* ENABLE (1 enable) | LOCKED (1 locked) */
108 /* FSEL | MDIV | PDIV | SDIV */
109 /* [27] | [25:16] | [13:8] | [2:0] */
110 writel(0xa0c80604, &clk->apll_con0);
112 /* Change CPU0 clock divider */
113 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
114 /* [30:28] | [26:24] | [22:20] | [18:16] */
115 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
116 /* [14:12] | [10:8] | [6:4] | [2:0] */
117 writel(0x00000100, &clk->div_cpu0);
119 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
120 while (readl(&clk->div_stat_cpu0) & 0x1111111)
123 /* Change clock divider ratio for DMC */
124 /* DMCP_RATIO | DMCD_RATIO */
125 /* [22:20] | [18:16] */
126 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
127 /* [14:12] | [10:8] | [6:4] | [2:0] */
128 writel(0x13113117, &clk->div_dmc0);
130 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
131 while (readl(&clk->div_stat_dmc0) & 0x11111111)
134 /* Turn off unnecessary power domains */
135 writel(0x0, &pwr->xxti_configuration); /* XXTI */
136 writel(0x0, &pwr->cam_configuration); /* CAM */
137 writel(0x0, &pwr->tv_configuration); /* TV */
138 writel(0x0, &pwr->mfc_configuration); /* MFC */
139 writel(0x0, &pwr->g3d_configuration); /* G3D */
140 writel(0x0, &pwr->gps_configuration); /* GPS */
141 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
143 /* Turn off unnecessary clocks */
144 writel(0x0, &clk->gate_ip_cam); /* CAM */
145 writel(0x0, &clk->gate_ip_tv); /* TV */
146 writel(0x0, &clk->gate_ip_mfc); /* MFC */
147 writel(0x0, &clk->gate_ip_g3d); /* G3D */
148 writel(0x0, &clk->gate_ip_image); /* IMAGE */
149 writel(0x0, &clk->gate_ip_gps); /* GPS */
152 static int pmic_init_max8997(void)
154 struct pmic *p = pmic_get("MAX8997_PMIC");
161 /* BUCK1 VARM: 1.2V */
162 val = (1200000 - 650000) / 25000;
163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
164 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
165 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
167 /* BUCK2 VINT: 1.1V */
168 val = (1100000 - 650000) / 25000;
169 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
170 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
171 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
174 /* BUCK3 G3D: 1.1V - OFF */
175 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
177 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
179 val = (1100000 - 750000) / 50000;
180 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
182 /* BUCK4 CAMISP: 1.2V - OFF */
183 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
185 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
187 val = (1200000 - 650000) / 25000;
188 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
190 /* BUCK5 VMEM: 1.2V */
191 val = (1200000 - 650000) / 25000;
192 for (i = 0; i < 8; i++)
193 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
195 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
196 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
198 /* BUCK6 CAM AF: 2.8V */
199 /* No Voltage Setting Register */
202 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
204 /* BUCK7 VCC_SUB: 2.0V */
205 val = (2000000 - 750000) / 50000;
206 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
208 /* LDO1 VADC: 3.3V */
209 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
210 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
212 /* LDO1 Disable active discharging */
213 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
215 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
217 /* LDO2 VALIVE: 1.1V */
218 val = max8997_reg_ldo(1100000) | EN_LDO;
219 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
221 /* LDO3 VUSB/MIPI: 1.1V */
222 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
223 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
225 /* LDO4 VMIPI: 1.8V */
226 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
227 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
229 /* LDO5 VHSIC: 1.2V */
230 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
231 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
233 /* LDO6 VCC_1.8V_PDA: 1.8V */
234 val = max8997_reg_ldo(1800000) | EN_LDO;
235 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
237 /* LDO7 CAM_ISP: 1.8V */
238 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
239 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
241 /* LDO8 VDAC/VUSB: 3.3V */
242 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
243 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
245 /* LDO9 VCC_2.8V_PDA: 2.8V */
246 val = max8997_reg_ldo(2800000) | EN_LDO;
247 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
249 /* LDO10 VPLL: 1.1V */
250 val = max8997_reg_ldo(1100000) | EN_LDO;
251 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
253 /* LDO11 TOUCH: 2.8V */
254 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
255 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
257 /* LDO12 VTCAM: 1.8V */
258 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
259 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
261 /* LDO13 VCC_3.0_LCD: 3.0V */
262 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
263 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
265 /* LDO14 MOTOR: 3.0V */
266 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
267 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
269 /* LDO15 LED_A: 2.8V */
270 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
271 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
273 /* LDO16 CAM_SENSOR: 1.8V */
274 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
275 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
277 /* LDO17 VTF: 2.8V */
278 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
279 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
281 /* LDO18 TOUCH_LED 3.3V */
282 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
283 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
285 /* LDO21 VDDQ: 1.2V */
286 val = max8997_reg_ldo(1200000) | EN_LDO;
287 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
289 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
290 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
291 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
292 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
295 puts("MAX8997 PMIC setting error!\n");
301 int power_init_board(void)
304 struct power_battery *pb;
305 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
307 ret = pmic_init(I2C_5);
308 ret |= pmic_init_max8997();
309 ret |= power_fg_init(I2C_9);
310 ret |= power_muic_init(I2C_5);
311 ret |= power_bat_init(0);
315 p_fg = pmic_get("MAX17042_FG");
317 puts("MAX17042_FG: Not found\n");
321 p_chrg = pmic_get("MAX8997_PMIC");
323 puts("MAX8997_PMIC: Not found\n");
327 p_muic = pmic_get("MAX8997_MUIC");
329 puts("MAX8997_MUIC: Not found\n");
333 p_bat = pmic_get("BAT_TRATS");
335 puts("BAT_TRATS: Not found\n");
339 p_fg->parent = p_bat;
340 p_chrg->parent = p_bat;
341 p_muic->parent = p_bat;
343 p_bat->low_power_mode = trats_low_power_mode;
344 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
347 chrg = p_muic->chrg->chrg_type(p_muic);
348 debug("CHARGER TYPE: %d\n", chrg);
350 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
351 puts("No battery detected\n");
355 p_fg->fg->fg_battery_check(p_fg, p_bat);
357 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
358 puts("CHARGE Battery !\n");
365 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
366 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
367 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
368 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
373 void dram_init_banksize(void)
375 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
376 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
377 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
378 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
379 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
380 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
381 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
382 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
385 static unsigned int get_hw_revision(void)
387 struct exynos4_gpio_part1 *gpio =
388 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
392 /* hw_rev[3:0] == GPE1[3:0] */
393 for (i = 0; i < 4; i++) {
394 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
395 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
400 for (i = 0; i < 4; i++)
401 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
403 debug("hwrev 0x%x\n", hwrev);
408 static void check_hw_revision(void)
412 hwrev = get_hw_revision();
417 #ifdef CONFIG_DISPLAY_BOARDINFO
420 puts("Board:\tTRATS\n");
425 #ifdef CONFIG_GENERIC_MMC
426 int board_mmc_init(bd_t *bis)
428 struct exynos4_gpio_part2 *gpio =
429 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
432 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
433 s5p_gpio_direction_output(&gpio->k0, 2, 1);
434 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
438 * mmc0 : eMMC (8-bit buswidth)
439 * mmc2 : SD card (4-bit buswidth)
441 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
443 debug("SDMMC0 not configured\n");
445 err = s5p_mmc_init(0, 8);
448 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
449 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
452 * Check the T-flash detect pin
453 * GPX3[4] T-flash detect pin
455 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
456 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
458 debug("SDMMC2 not configured\n");
460 err = s5p_mmc_init(2, 4);
467 #ifdef CONFIG_USB_GADGET
468 static int s5pc210_phy_control(int on)
472 struct pmic *p = pmic_get("MAX8997_PMIC");
480 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
482 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
483 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
485 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
486 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
488 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
489 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
491 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
492 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
493 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
494 ENSAFEOUT1, LDO_OFF);
498 puts("MAX8997 LDO setting error!\n");
505 struct s3c_plat_otg_data s5pc210_otg_data = {
506 .phy_control = s5pc210_phy_control,
507 .regs_phy = EXYNOS4_USBPHY_BASE,
508 .regs_otg = EXYNOS4_USBOTG_BASE,
509 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
510 .usb_flags = PHY0_SLEEP,
513 void board_usb_init(void)
515 debug("USB_udc_probe\n");
516 s3c_udc_probe(&s5pc210_otg_data);
520 static void pmic_reset(void)
522 struct exynos4_gpio_part2 *gpio =
523 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
525 s5p_gpio_direction_output(&gpio->x0, 7, 1);
526 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
529 static void board_clock_init(void)
531 struct exynos4_clock *clk =
532 (struct exynos4_clock *)samsung_get_base_clock();
534 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
535 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
536 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
537 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
539 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
540 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
541 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
542 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
543 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
544 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
545 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
546 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
547 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
548 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
549 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
550 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
552 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
553 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
554 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
555 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
556 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
557 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
558 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
559 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
560 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
561 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
562 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
563 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
565 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
566 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
567 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
568 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
569 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
570 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
571 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
572 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
573 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
574 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
575 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
576 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
579 static void board_power_init(void)
581 struct exynos4_power *pwr =
582 (struct exynos4_power *)samsung_get_base_power();
585 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
588 writel(0, (unsigned int)&pwr->cam_configuration);
589 writel(0, (unsigned int)&pwr->tv_configuration);
590 writel(0, (unsigned int)&pwr->mfc_configuration);
591 writel(0, (unsigned int)&pwr->g3d_configuration);
592 writel(0, (unsigned int)&pwr->lcd1_configuration);
593 writel(0, (unsigned int)&pwr->gps_configuration);
594 writel(0, (unsigned int)&pwr->gps_alive_configuration);
596 /* It is necessary to power down core 1 */
597 /* to successfully boot CPU1 in kernel */
598 writel(0, (unsigned int)&pwr->arm_core1_configuration);
601 static void board_uart_init(void)
603 struct exynos4_gpio_part1 *gpio1 =
604 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
605 struct exynos4_gpio_part2 *gpio2 =
606 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
611 * GPA1CON[0] = UART_2_RXD(2)
612 * GPA1CON[1] = UART_2_TXD(2)
613 * GPA1CON[2] = I2C_3_SDA (3)
614 * GPA1CON[3] = I2C_3_SCL (3)
617 for (i = 0; i < 4; i++) {
618 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
619 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
622 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
623 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
624 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
627 int board_early_init_f(void)
638 static void lcd_reset(void)
640 struct exynos4_gpio_part2 *gpio2 =
641 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
643 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
645 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
647 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
650 static int lcd_power(void)
653 struct pmic *p = pmic_get("MAX8997_PMIC");
660 /* LDO15 voltage: 2.2v */
661 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
662 /* LDO13 voltage: 3.0v */
663 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
666 puts("MAX8997 LDO setting error!\n");
673 static struct mipi_dsim_config dsim_config = {
674 .e_interface = DSIM_VIDEO,
675 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
676 .e_pixel_format = DSIM_24BPP_888,
677 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
678 .e_no_data_lane = DSIM_DATA_LANE_4,
679 .e_byte_clk = DSIM_PLL_OUT_DIV8,
686 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
687 .pll_stable_time = 500,
689 /* escape clk : 10MHz */
690 .esc_clk = 20 * 1000000,
692 /* stop state holding counter after bta change count 0 ~ 0xfff */
693 .stop_holding_cnt = 0x7ff,
694 /* bta timeout 0 ~ 0xff */
696 /* lp rx timeout 0 ~ 0xffff */
697 .rx_timeout = 0xffff,
700 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
701 .lcd_panel_info = NULL,
702 .dsim_config = &dsim_config,
705 static struct mipi_dsim_lcd_device mipi_lcd_device = {
709 .platform_data = (void *)&s6e8ax0_platform_data,
712 static int mipi_power(void)
715 struct pmic *p = pmic_get("MAX8997_PMIC");
722 /* LDO3 voltage: 1.1v */
723 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
724 /* LDO4 voltage: 1.8v */
725 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
728 puts("MAX8997 LDO setting error!\n");
735 vidinfo_t panel_info = {
741 .vl_clkp = CONFIG_SYS_HIGH,
742 .vl_hsp = CONFIG_SYS_LOW,
743 .vl_vsp = CONFIG_SYS_LOW,
744 .vl_dp = CONFIG_SYS_LOW,
745 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
747 /* s6e8ax0 Panel infomation */
755 .vl_cmd_allow_len = 0xf,
759 .backlight_on = NULL,
760 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
761 .reset_lcd = lcd_reset,
762 .dual_lcd_enabled = 0,
767 .interface_mode = FIMD_RGB_INTERFACE,
771 void init_panel_info(vidinfo_t *vid)
774 vid->resolution = HD_RESOLUTION,
775 vid->rgb_mode = MODE_RGB_P,
778 get_tizen_logo_info(vid);
782 mipi_lcd_device.reverse_panel = 1;
784 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
785 s6e8ax0_platform_data.lcd_power = lcd_power;
786 s6e8ax0_platform_data.mipi_power = mipi_power;
787 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
788 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
789 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
791 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
793 setenv("lcdinfo", "lcd=s6e8ax0");
796 #ifdef CONFIG_USB_GADGET_MASS_STORAGE
797 static int ums_read_sector(struct ums_device *ums_dev,
798 ulong start, lbaint_t blkcnt, void *buf)
800 if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num,
801 start + ums_dev->offset, blkcnt, buf) != blkcnt)
807 static int ums_write_sector(struct ums_device *ums_dev,
808 ulong start, lbaint_t blkcnt, const void *buf)
810 if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num,
811 start + ums_dev->offset, blkcnt, buf) != blkcnt)
817 static void ums_get_capacity(struct ums_device *ums_dev,
818 long long int *capacity)
820 long long int tmp_capacity;
822 tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size)
824 *capacity = ums_dev->mmc->capacity - tmp_capacity;
827 static struct ums_board_info ums_board = {
828 .read_sector = ums_read_sector,
829 .write_sector = ums_write_sector,
830 .get_capacity = ums_get_capacity,
831 .name = "TRATS UMS disk",
840 struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset,
841 unsigned int part_size)
845 mmc = find_mmc_device(dev_num);
849 ums_board.ums_dev.mmc = mmc;
850 ums_board.ums_dev.dev_num = dev_num;
851 ums_board.ums_dev.offset = offset;
852 ums_board.ums_dev.part_size = part_size;