2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
3 * Sanghee Kim <sh0130.kim@samsung.com>
4 * Piotr Wilczek <p.wilczek@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/mmc.h>
14 #include <asm/arch/power.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/mipi_dsim.h>
18 #include <asm/arch/pinmux.h>
19 #include <asm/arch/power.h>
20 #include <power/pmic.h>
21 #include <power/max77686_pmic.h>
22 #include <power/battery.h>
23 #include <power/max77693_pmic.h>
24 #include <power/max77693_muic.h>
25 #include <power/max77693_fg.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 static struct exynos4x12_gpio_part1 *gpio1;
32 static struct exynos4x12_gpio_part2 *gpio2;
34 static unsigned int board_rev = -1;
36 static inline u32 get_model_rev(void);
38 static void check_hw_revision(void)
43 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
46 * GPM1[1:0]: MODEL_REV[1:0]
47 * Don't set as pull-none for these N/C pin.
48 * TRM say that it may cause unexcepted state and leakage current.
49 * and pull-none is only for output function.
51 for (i = 0; i < 2; i++)
52 s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
54 /* GPM1[5:2]: HW_REV[3:0] */
55 for (i = 2; i < 6; i++) {
56 s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
57 s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE);
60 /* GPM1[1:0]: MODEL_REV[1:0] */
61 for (i = 0; i < 2; i++)
62 modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i);
64 /* board_rev[15:8] = model */
65 board_rev = modelrev << 8;
68 #ifdef CONFIG_DISPLAY_BOARDINFO
71 puts("Board:\tTRATS2\n");
76 static void show_hw_revision(void)
78 printf("HW Revision:\t0x%04x\n", board_rev);
81 u32 get_board_rev(void)
86 static inline u32 get_model_rev(void)
88 return (board_rev >> 8) & 0xff;
91 static void board_external_gpio_init(void)
93 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
96 * some pins which in alive block are connected with external pull-up
97 * but it's default setting is pull-down.
98 * if that pin set as input then that floated
101 s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */
102 s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */
103 s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
104 s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
105 s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */
106 s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */
107 s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */
108 s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */
109 s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */
110 s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */
111 s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */
112 s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */
115 #ifdef CONFIG_SYS_I2C_INIT_BOARD
116 static void board_init_i2c(void)
120 gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
121 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
124 err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
126 debug("I2C%d not configured\n", (I2C_7));
131 s5p_gpio_direction_output(&gpio1->f1, 4, 1);
132 s5p_gpio_direction_output(&gpio1->f1, 5, 1);
135 s5p_gpio_direction_output(&gpio2->m2, 1, 1);
136 s5p_gpio_direction_output(&gpio2->m2, 0, 1);
140 #ifdef CONFIG_SYS_I2C_SOFT
141 int get_soft_i2c_scl_pin(void)
144 return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
146 return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
149 int get_soft_i2c_sda_pin(void)
152 return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
154 return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
158 int board_early_init_f(void)
161 board_external_gpio_init();
163 gd->flags |= GD_FLG_DISABLE_CONSOLE;
168 static int pmic_init_max77686(void);
172 struct exynos4_power *pwr =
173 (struct exynos4_power *)EXYNOS4X12_POWER_BASE;
175 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
177 /* workaround: clear INFORM4..5 */
178 writel(0, (unsigned int)&pwr->inform4);
179 writel(0, (unsigned int)&pwr->inform5);
184 int power_init_board(void)
187 struct power_battery *pb;
188 struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
190 #ifdef CONFIG_SYS_I2C_INIT_BOARD
193 pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */
194 pmic_init_max77686();
195 pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */
196 power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */
197 power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */
200 p_chrg = pmic_get("MAX77693_PMIC");
202 puts("MAX77693_PMIC: Not found\n");
206 p_muic = pmic_get("MAX77693_MUIC");
208 puts("MAX77693_MUIC: Not found\n");
212 p_fg = pmic_get("MAX77693_FG");
214 puts("MAX17042_FG: Not found\n");
218 if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0)
219 puts("No battery detected\n");
221 p_bat = pmic_get("BAT_TRATS2");
223 puts("BAT_TRATS2: Not found\n");
227 p_fg->parent = p_bat;
228 p_chrg->parent = p_bat;
229 p_muic->parent = p_bat;
231 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
234 chrg = p_muic->chrg->chrg_type(p_muic);
235 debug("CHARGER TYPE: %d\n", chrg);
237 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
238 puts("No battery detected\n");
242 p_fg->fg->fg_battery_check(p_fg, p_bat);
244 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
245 puts("CHARGE Battery !\n");
254 size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
255 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
256 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
257 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
259 gd->ram_size = size_mb << 20;
264 void dram_init_banksize(void)
266 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
267 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
268 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
269 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
270 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
271 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
272 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
273 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
276 int board_mmc_init(bd_t *bis)
280 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
282 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
283 s5p_gpio_direction_output(&gpio2->k0, 2, 1);
284 s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
288 * SDR 8-bit@48MHz at MMC0
289 * GPK0[0] SD_0_CLK(2)
290 * GPK0[1] SD_0_CMD(2)
291 * GPK0[2] SD_0_CDn -> Not used
292 * GPK0[3:6] SD_0_DATA[0:3](2)
293 * GPK1[3:6] SD_0_DATA[0:3](3)
295 * DDR 4-bit@26MHz at MMC4
296 * GPK0[0] SD_4_CLK(3)
297 * GPK0[1] SD_4_CMD(3)
298 * GPK0[2] SD_4_CDn -> Not used
299 * GPK0[3:6] SD_4_DATA[0:3](3)
300 * GPK1[3:6] SD_4_DATA[4:7](4)
303 err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
307 * mmc0 : eMMC (8-bit buswidth)
308 * mmc2 : SD card (4-bit buswidth)
311 debug("SDMMC0 not configured\n");
313 err0 = s5p_mmc_init(0, 8);
316 s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
317 s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
320 * Check the T-flash detect pin
321 * GPX3[4] T-flash detect pin
323 if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
324 err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
326 debug("SDMMC2 not configured\n");
328 err2 = s5p_mmc_init(2, 4);
334 static int pmic_init_max77686(void)
336 struct pmic *p = pmic_get("MAX77686_PMIC");
341 /* BUCK/LDO Output Voltage */
342 max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */
343 max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/
344 max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */
346 /* BUCK/LDO Output Mode */
347 max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */
348 max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */
349 max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */
350 max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */
351 max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */
352 max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/
353 max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */
354 max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */
355 max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/
357 max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/
358 max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */
359 max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */
360 max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */
361 max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */
362 max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */
363 max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */
364 max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */
365 max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/
366 max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/
367 max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/
368 max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/
369 max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */
370 max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */
371 max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/
372 max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/
373 max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/
374 max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/
375 max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */
376 max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/
377 max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */
378 max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/
379 max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/
380 max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */
381 max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */
382 max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/
392 static struct mipi_dsim_config dsim_config = {
393 .e_interface = DSIM_VIDEO,
394 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
395 .e_pixel_format = DSIM_24BPP_888,
396 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
397 .e_no_data_lane = DSIM_DATA_LANE_4,
398 .e_byte_clk = DSIM_PLL_OUT_DIV8,
405 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
406 .pll_stable_time = 500,
408 /* escape clk : 10MHz */
409 .esc_clk = 20 * 1000000,
411 /* stop state holding counter after bta change count 0 ~ 0xfff */
412 .stop_holding_cnt = 0x7ff,
413 /* bta timeout 0 ~ 0xff */
415 /* lp rx timeout 0 ~ 0xffff */
416 .rx_timeout = 0xffff,
419 static struct exynos_platform_mipi_dsim dsim_platform_data = {
420 .lcd_panel_info = NULL,
421 .dsim_config = &dsim_config,
424 static struct mipi_dsim_lcd_device mipi_lcd_device = {
428 .platform_data = (void *)&dsim_platform_data,
431 static int mipi_power(void)
433 struct pmic *p = pmic_get("MAX77686_PMIC");
435 /* LDO8 VMIPI_1.0V_AP */
436 max77686_set_ldo_mode(p, 8, OPMODE_ON);
437 /* LDO10 VMIPI_1.8V_AP */
438 max77686_set_ldo_mode(p, 10, OPMODE_ON);
443 void exynos_lcd_power_on(void)
445 struct pmic *p = pmic_get("MAX77686_PMIC");
447 gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
449 /* LCD_2.2V_EN: GPC0[1] */
450 s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
451 s5p_gpio_direction_output(&gpio1->c0, 1, 1);
453 /* LDO25 VCC_3.1V_LCD */
455 max77686_set_ldo_voltage(p, 25, 3100000);
456 max77686_set_ldo_mode(p, 25, OPMODE_LPM);
459 void exynos_reset_lcd(void)
461 gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
464 s5p_gpio_direction_output(&gpio1->f2, 1, 0);
466 s5p_gpio_set_value(&gpio1->f2, 1, 1);
469 vidinfo_t panel_info = {
475 .vl_clkp = CONFIG_SYS_HIGH,
476 .vl_hsp = CONFIG_SYS_LOW,
477 .vl_vsp = CONFIG_SYS_LOW,
478 .vl_dp = CONFIG_SYS_LOW,
479 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
481 /* s6e8ax0 Panel infomation */
489 .vl_cmd_allow_len = 0xf,
492 .dual_lcd_enabled = 0,
495 .power_on_delay = 25,
497 .interface_mode = FIMD_RGB_INTERFACE,
500 void init_panel_info(vidinfo_t *vid)
503 vid->resolution = HD_RESOLUTION;
504 vid->rgb_mode = MODE_RGB_P;
506 vid->power_on_delay = 30;
508 mipi_lcd_device.reverse_panel = 1;
511 get_tizen_logo_info(vid);
514 strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
515 dsim_platform_data.mipi_power = mipi_power;
516 dsim_platform_data.phy_enable = set_mipi_phy_ctrl;
517 dsim_platform_data.lcd_panel_info = (void *)vid;
518 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
522 exynos_set_dsim_platform_data(&dsim_platform_data);
526 #ifdef CONFIG_MISC_INIT_R
527 int misc_init_r(void)
529 setenv("model", "GT-I8800");
530 setenv("board", "TRATS2");